Mixed-Signal Integrated Circuits and Systems Lab
News
Prof. Musah successfully completed his maiden edition of PREFACE 2.0 Workshop on Hardware Security.
Posted August 20, 2022
Prof. Musah revisits the microchip shortage and discuses Intel in Ohio with 10TV News.
Posted May 22, 2022
Clay Gordon of 10 TV News discusses the impact of microchip shortage on future innovation in the auto industry.
Mohamed Ahmed Awarded ISCAS 2022 Student Participation Grant
Posted April 15, 2022
Congratulations to Mohamed for getting awarded the ISCAS student participation grant for 2022. He will be presenting a paper on characterization of sub-Nyquist TIAs with equalization in optical receivers.
Mohamed Abouzeid Successfully Defends his MS Thesis
Posted: October 05, 2021
Congratulations to Kevin Du for successfully defending his thesis on time domain MAC engines for convolutional neural networks.
Prof. Musah talks to 10TV about microchip shortage
Posted July 22, 2021
Clay Gordon of 10 TV News discusses the impact of microchip shortage on car prices.
Kevin Successfully Defends his MS Thesis
Posted: December 04, 2020
Congratulations to Kevin Du for successfully defending his thesis on time domain MAC engines for convolutional neural networks.
Abishek Successfully Defends his MS Thesis
Posted: April 17, 2020
Congratulations to Abishek Namachivayam for successfully defending his thesis on high speed clock and data recovery.
Recognition of Teaching
Posted: February 10, 2020
Prof. Musah was recognized with an Outstanding Teaching Award for the Autumn 2019 semester.
Abishek Wins Outstanding GTA Award
Posted: January 15, 2020
Congratulations to Abishek Namachivayam for being recognized as an outstanding graduate teaching assistant (GTA) for Autumn 2019 semester.
Mohamed Passes Qualifying Exam
Posted: November 7, 2019
Congratulations to Mohamed Abouzeid for passing his qualifying exam.
Recognition of Teaching
Posted: August 26, 2019
Prof. Musah was recognized with an Outstanding Teaching Award for the Spring 2019 semester.
Faculty Spotlight
Posted: September 11, 2018
A spotlight on Prof. Musah in ECE Weekly Newsletter
Prof. Musah Joins OSU's Dept. of ECE
Posted: January 2, 2018
Prof. Musah joins the Electrical and Computer Engineering Department at the Ohio State University in Spring of 2018.
Research
With the steep increase in aggregate I/O bandwidth demands, higher per lane bandwidths are required over existing channels. The resulting increase in channel loss can be overcome in multiple ways; all of which lead to more equalization complexity. In past projects, innovative timing recovery schemes where used to drive simpler equalizers at the receiver [MusahJSSC14, MusahPatent19, VenkatramPatent17]. In this research thrust, we investigate new transceiver architectures that enable enhanced equalization without increase in complexity over a wide range of applications and use cases.
Sponsor: Intel Corporation
Digital receiver equalizers have become the go to equalization architectures for high loss channels. One of the reasons for this is that they obviate the trade-off between number of DFE taps and data rate. Also, they enable multi-standard use of the hardware due to their high programmability. Moreover, the highly digital designs they enable can be easily ported from one technology to another. However, current ADC-based receiver designs still lag their mixed-mode counterparts in power and area efficiency. A major cause of this power efficiency gap is the complexity of the analog-to-digital converter (ADC) in the front-end. In this research thrust, we combine our extensive prior work on ADCs [see MusahCICC09, RajaeeJSSC10] with serial I/O system expertise to explore new digital receiver topologies that yield higher area and power efficiencies.
Active Sponsors:
OSU CoE
Past Sponsors:
Asahi Kasei Microdevices (AKM)
The demand for aggregate bandwidth for network and accelerator applications has lead to a steep rise in per lane data rates across the board for I/O standards. As can be seen in the Fig. 1 below, beyond the increase in per lane data rates, there is an industry drive towards the same data rates across standards. This streamlines I/O convergence efforts, at least at the transceiver architecture level. A collection of the transceiver architectural choices in each of prevailing wireline link standards will be presented below (TBD), highlighting approaches to signaling, clocking, equalization and timing recovery. The mode of communication (electrical vs optical) and modulation schemes will also be catalogued.
Team Members
- Ahmed Abdel Aziz, PhD Candidate, Joined Autumn 2019, Low Complexity Receivers for Optical Applications
- Mohamed Radwan Ahmed, PhD Student, Joined Autumn 2020, Optical Transceiver Circuits
- Graduate Fellow, PhD Student, Joined Summer 2021, Physical Layer Security for Automotive Wireline Applications
- Jeffery Asare Boateng, PhD Student, Joined Summer 2023, Advanced Signaling & Coding for Wireline Applications
- Siddharth Venkatesan, Undergraduate Student Researcher, FPGA
- Ariana Clealand, Undergraduate Researcher, BS Graduated, Hardware based design/modeling environment using PYNQ-Z2.
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- Mohamed Abouzeid, MS Graduated, Low Complexity Receivers for Optical Applications
- Kevin Du, MS, Graduate December 2020, Currently with Xilinx
- Abishek Namachivayam, MS, Graduated May 2020, Currently with Micron
Cad Tutorials
Video
Please watch the remote access and virtuoso setup video if your prefer that to the instructions below.
1. Environment Setup and Cadence Virtuoso Startup
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Log into of the following servers (rh053, rh054, rh055). These are the only servers you can use for class work.
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From the Linux Desktop, open a new Terminal (Applications >> System Tools >> Terminal)
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In your home directory, create a new directory called “cadence” . If you already have a “cadence” directory, then ignore this step.
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mkdir cadence
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Change directory to “cadence”, then create and change to a new directory called “ECE5020”
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cd cadence
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mkdir ECE5020
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cd ECE5020
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Source the cadence environment setup file
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source /opt/local/cadence/class/ece5020/virtuoso_initial_setup
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Switch your shell to tcsh, source cadence parameters and launch virtuoso
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tcsh
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source launch.cadence
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virtuoso &
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A new Virtuoso window should open
2. Creating a new library
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From the Command Interpreter Window (CIW) - pictured above, goto Tools >> Library Manager. The library manager will display all the technology libraries and cells. Select one library and check "Show Categories" and "Show Files" to see its contents.
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In the library manger, go to the menu “File >> New >> Library”
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Type the desired name of your new library, for example “mydesign”. Leave the directory at the default, then click OK. Select “Attach to an existing technology library” under Technology File, then press OK. A new window asking for the technology Library for your new library will show up. Select “gpdk045” and press OK
3. Routine Use
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Change directory to “ECE5020”
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cd ~/cadence/ECE5020
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Switch your shell to tcsh, source cadence parameters and launch virtuoso
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tcsh
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source launch.cadence
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virtuoso
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Video
Please watch the NMOS DC Simulation video if you prefer that to the instructions below.
1. How to Run DC Simulations
Start Cadence using the previous setup instructions
In the Library Manager, select the previous created design library. Create a new schematic by going to "File >> New >> Cell View". A new file window will open. Choose a descriptive name for your schematic and click OK.
Create a 0V voltage source using "Create >> Instance" as shown below. Drop the instance in your schematic cell view. Repeat to create 3 more ("0V", "VGS" and "VDS").
Add a transistor instance with the parameters shown below
Connect the instances using add wires and labels ("Create >> Wire (narrow)" and "Create >> Wire Name")
Goto File >> Check and Save to save your schematic.
To simulate your schematic, open the Analog Design Environment by going to "Launch >> ADE L."
Copy the schematic variables into the ADE L by going to "Variables >> Copy From Cellview." Set the value of both VDS and VGS to 1.
Setup a DC sweep as shown below ("Analyses >> Choose").
Choose the signals that you need to be saved by selecting the desired wires and terminal currents on the schematic as shown below
Click on the checkbox next to M1/D to plot the drain current and hit the green play button to netlist and run your testbench. The results should like shown below.
For nested DC sweep, run parameteric analysis on your results ("Tools >> Parametric Analysis"). Sweep VGS as shown in the image below.
The result of your nested DC simulation should look like shown below.
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Video
Please watch this video for the inverter schematics, symbol, testbench, loading and transient simulation setup.
In this tutorial, we will create an inverter schematic, symbol and a testbench to run a transient simulation on the inverter schematic.
Schematic and Symbol Creation
Make a new cellview as in the "Run DC simulations" case and name it "inv." Build the inverter schematic as shown below:
Add pins from "Create >> Pin". Choose input direction for (in, vdd, vss) and output direction for (out). Save your work.
To create a symbol for the schematic go to "Create >> Cellview >> From Cellview", click OK on the next two popup windows.
Edit the the symbol into something more representative of the schematic. (m, M to move, s to stretch, r to rotate, and line, and shapes in the tool bar). An edited version of the inverter symbol is shown below. Check&Save your symbol.
Transient Simulation Testbench
Make a new schematic cellview and name it "inv_test." Bring in the inverter symbol you created in the previous step using "Create >> Instance." Add 1V and 0V DC source lik in the "Run DC simulations." A a transient pulse source and set up its parameters as shown below.
Add a capictive load on the inverter, and use "cload" a variable for the capacitor value.
Launch ADE L and copy the simulation variables in (Variables >> Copy From Cellview) and set the load capicitance to 10f and period to 500p.
Choose a transient analysis (Analyses >> Choose) and set it up as shown below. Save "vin" and "vout" and select it to plot too.
The simulated resulted should look the waveforms below.
Save this simulation state ("Session >> Save State") and choose a descriptive name for this state and hit OK.
DC VTC Simulation
In the inv_test schematic view, add a DC source with a value "dcin." Label its out "vindc" and switch the inverter input label to same node.
In ADE L, add the new node "vindc" to saved outputs and deselect vin from plot and copy "dcin" from the cellview set it to 0.
Add a DC analysis to ADE L and set it up as shown below. Click OK. Disable the transient simulation.
Run the simulation, and the result will show the inverter VTC as below
To see the gain of the inverter, you can use the calculator to find the derivative of the dc output. ("Tools >> Calculator"), Pick "vs" and select "out" from the schematic. In the Function Panel of the Calculator, choose "deriv" and hit plot
This page was originally created by Kevin Du. It provides an introductory rundown on the NCLaunch portion of the Incisive Enterprise Simulator (IES).
Table Of Contents
Startup
Create a directory for Incisive in which you will run the simulator, and navigate into it.
$ mkdir incisive $ cd incisive
Create a startup script.
$ vi startup.incisive.152
Paste the contents of the script below into the file.
setenv CDS_BASE_DIR /opt/local/cadence/cad
setenv CDS_LIC_DIR /opt/local/cadence/etc
setenv CDS_LIC_FILE ${CDS_LIC_DIR}/license.dat
setenv PATH ${PATH}:/opt/local/cadence/cad/INCISIVE152/tools/bin/64bit:/opt/local/cadence/cad/INCISIVE152/tools/bin
Now source it in a tcsh.
$ tcsh % source incisive.startup.152
This script configures the Cadence base directory, license directory, and license file so that a copy of Incisive can be checked out. It then appends to the $PATH variable the path to the Incisive binaries.
Note: This script launches Incisive in 64bit mode.
Once the path is updated, you can run IES through the nclaunch command.
% nclaunch&
Once IES starts, you should see an option to select the run mode. Select Multiple-Step.
Single step bundles the ncvlog compiler, ncelab elaborator, and ncsim simvision simulator into a single command named IRUN. I've experienced some weird caching issues with IRUN, so this guide will be using the multi-step tool.
In IES, you should see on the left the file browser, and a virtual library managed by a cds.lib on the right.
On the top, there will be a tools menu that the various binaries can be invoked with.
Compiling Verilog
Verilog source files can be compiled by using the Verilog Compiler... option in the tool menu.
Navigate in the file browser to the source files you want to compile.
Select them either individually or using ctrl click, then invoke the Tools -> Verilog Compiler...
Source files will be compiled into the virtual library, under the folder specified as the "work library". You can change which work library you would like to compile into through the dropdown menu.
Note: The dropdown menu will always default to what is specified as the default work library every time theVerilog Compiler...is invoked. The default work library can be configured by right clicking on a library and selectingset as work library.
Your files now show up on the right, in the specified work library (default worklib).
If you are doing behavioral simulation, skip to Elaboration
Create a new library for compiling standard cells to through Edit -> Add -> New Library....
This is to contain all the cells within a separate library that you won't have to look at. This allows you to find the modules you care about faster, as only IES cares about the cells, and displaying 400 objects in the GUI is extremely laggy.
Compile the fast_vdd1v0_basicCells.v file to the newly created library.
You can find this file under the verilog folder inside of the standard cell library that you used for Genus. Use the same file that you used as the library, just with a .v instead of a .lib extension.
Expand the library to verify that the cells are properly compiled.
Elaboration
Expand the work library that your source files were compiled to, and expand the hierarchy of the stimulus file.
Select the top level module, and invoke Tools -> Elaborator....
In the options menu, enable Other Options; specify -timescale 1ns/1ns -sdf_verbose.
The timescale option sets the default timescale for the simulator to use if a module doesn't have a timescale specified. This prevents the timescale undefined error, which occurs because IES requires all modules to have timescales defined.
The -sdf_verbose option forces the SDF annotator to log all annotated delays to the log file.
You should have created an SDF file at the end of your Genus run. Inside of your stimulus block you can use the $sdf_annotate system directive to perform automatic back annotations during elaboration.
$sdf_annotate ( “sdf_file” {, module_instance} {, “config_file”}
{, “log_file”} {, “mtm_spec”}
{, “scale_factors”} {, “scale_type”} );
The arguments are as follows.
"sdf_file"
Specifies the path to the SDF file. Relative file paths, i.e
"~/genus/alu.sdf" can be used.
The path must be in quotes.
The SDF file can be in four different formats:
Source - alu.sdf
Compiled - alu.sdf.X
Zipped - alu.sdf.gz
Zipped & Compiled - alu.sdf.gz.X
The file that Genus outputs is SDF source, using this is fine, as the
ncsdfc will automatically compile the sdf file.
module_instance
Optional: Specifies the scope that the annotation takes place. If not
specified, the module containing the $sdf_annotate call will be set as
module_instance.
If this is not specified properly for a given SDF file, the elaborator will
log a very low percentage annotated.
"config_file"
Optional: Specifies a path to a configuration file to control the timing.
If you don't specify a config file, the annotator uses default settings.
The path must be in quotes.
For now, omit this.
"log_file"
Optional: Specifies a path to a log file. If you use this, you must supply
-sdf_verbose as an argument to the elaborator.
The path must be in quotes. If it is just a name, such as "sdf.log", it
will be placed in the IES launch directory.
"mtm_spec"
Optional: Specifies the delay values to annotate, in quotes, chosen from:
"MINIMUM" - annotates minimum delay value.
"TYPICAL" - annotates typical delay value.
"MAXIMUM" - annotates maximum delay value.
"TOOL_CONTROL" (default) - annotates from the command line option
specified.
If no command line options are specified, this defaults to TYPICAL.
If using GPDK045's timing files, you should specify "MAXIMUM", as
"TYPICAL" / "MINIMUM" causes the annotator to annotate blank values
since those timing values are blank, resulting in ideal timing.
"scale_factors"
Optional: Three positive real numbers that the SDF annotator uses to scale
the minimum, typical, and maximum delay values.
The syntax is "min_mult:typ_mult:max_mult"; the default is "1.0:1.0:1.0".
Specifying this will override the config file.
"scale_type"
Specifies how the annotator scales the timing specification, in quotes,
chosen from:
"FROM_MINIMUM" - scales from minimum timing specification.
"FROM_TYPICAL" - scales from typical timing specification.
"FROM_MAXIMUM" - scales from the maximum timing specification.
"FROM_MTM" (default) - scales from the minimum, typical, and
maximum timing specifications.
You can leave this as default.
Simulation
After elaborating, you should see an item under the snapshot library.
Expand this, select it, and invoke Tools -> Simulator.... You can leave the options default.
The simvision window should now pop up, and you can press F2 to simulate.
NCHelp
If you encounter a warning (*W) or error (*F) during any of the steps, you can run nchelp <step> <errCode> in the shell that IES was launched from to get a description of the error.
For example, if you encounter the *F,CUMSTS error during elaboration, you can get more info.
% nchelp ncelab cumsts nchelp: 15.20-s068: (c) Copyright 1995-2019 Cadence Design Systems, Inc. ncelab/cumsts = If any module has been compiled with a timescale directive, the elaborator requires that all modules be compiled with a timescale directive. Use the -messages flag to have the timescales for each module printed. Use -TIMESCALE option to provide a timescale directive for all modules that don't have one.
This page was originally created by Kevin Du. It provides an example introductory run of the Innovus Place & Route flow. It shows the commands to be run for an example netlist generated from the Genus tutorial, and briefly describes what each command does.
Table Of Contents
Startup
Timing Setup
Main Run
GUI
Timing
Design Checks
Saving
Startup
Create a directory (preferably next to your Genus folder), and navigate into it.
mkdir innovus cd innovus
Create a startup script.
$ vi startup.innovus.181
Copy & Paste the script below in the file
setenv CDS_BASE_DIR /opt/local/cadence/cad
setenv CDS_LIC_DIR /opt/local/cadence/etc
setenv CDS_LIC_FILE ${CDS_LIC_DIR}/license.dat
setenv PATH ${PATH}:/opt/local/cadence/cad/INNOVUS181/tools/bin
This script configures the Cadence base directory, license directory, and license file so that a copy of Genus can be checked out.
It then adds the path to the Innovus binaries to $PATH.
Navigate to your cadence home directory, where your cds.lib is located.
Create a file named .cdsinit (or edit the existing one) and add this to it.
load "/opt/local/cadence/cad/INNOVUS181/tools/innovus/gift/AoT/VEXface/virLaunchInnovusIC61x.il"
This tells the CIW to load virLaunchInnovusIC61x.il, which adds Innovus as an option under Layout XL.
Source the startup.innovus.181 file in a tcsh.
$ tcsh % source startup.innovus.181
Now relaunch Cadence Virtuoso, and open Virtuoso Layout XL
From the Launch-> dropdown menu, you should now see `Innovus` as an option. Select it.
Note: This option only appears on Virtuoso Layout XL or GXL. Layout L will not have it.
This box should now apppear. Innovus uses the process node for optimization purposes. For the purposes of this tutorial, the GUI options generated by this form will be ignored, as they are generally more verbose and contain additional features that aren't necessary to get a basic design working. If you choose to use this flow to generate your form, you can compare the resulting script to the one in this tutorial for debugging purposes. This will save the script to VDIRunScriptInn.tcl, which you can then modify.
Timing Setup
In order for Innovus to do timing analysis, constraints need to be supplied, similar to Genus.
The SDC file containing the constraints used in Genus to generate the netlist should be translated from Genus SDC syntax to the generic syntax using the write_sdc command at the end of the Genus flow.
Next, create a tcl script named design.view and edit it.
Change the directory in the script to somewhere that is close to the timing libraries and QX techfile.
Mine is symlinked, so it is in my cadence directory. You can do this with ln -s.
cd /home/du.566/cadence/GPDK45/
Create a constraint from an SDC file. The file supplied should be from the write_sdc output of your Genus run.
create_constraint_mode -name ALUConstraint -sdc_files [list synthesis/innovus/genus_outputs/ALUREG8bit.sdc]
Create an RC corner from the QX tech file.
create_rc_corner -name rc_typical -qx_tech_file gsclib045_all_v4.4/gsclib045_tech/qrc/qx/gpdk045.tch
Note: If you use the wrong file, you may get an unknown error along with a message to contact cadence. If this happens, try another file.
Create a library set for each timing corner.
create_library_set -name Slowlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v0_basicCells.lib}
create_library_set -name Fastlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v0_basicCells.lib}
create_library_set -name Slowlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v2_basicCells.lib}
create_library_set -name Fastlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v2_basicCells.lib}
Create delay corners associating a library set and RC corner.
Note: There's no point in doing this with a single RC corner, but with multiple you can create more delay corners.
This is still required though, as analysis views take delay corners.
create_delay_corner -name DCSlow -library_set {Slowlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCFast -library_set {Fastlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCSlow1v2 -library_set {Slowlib1v2} -rc_corner {rc_typical}
create_delay_corner -name DCFast1v2 -library_set {Fastlib1v2} -rc_corner {rc_typical}
Create analysis views associating a constraint (SDC), and a delay corner. This is the final result of this view file, as it binds timing constraints with best case / worst case post route timing information, allowing Innovus to perform timing analysis and optimization.
For Hold analysis, use the fast corner. For Setup, use the slow corner.
create_analysis_view -name setup -constraint_mode ALUConstraint -delay_corner {DCSlow}
create_analysis_view -name hold-constraint_mode ALUConstraint -delay_corner {DCFast}
create_analysis_view -name setup1v2 -constraint_mode ALUConstraint -delay_corner {DCSlow1v2}
create_analysis_view -name hold1v2 -constraint_mode ALUConstraint -delay_corner {DCFast1v2}
Finally, attach the analysis view for setup and hold analysis.
set_analysis_view -setup {setup setup1v2] -hold {hold hold1v2}
The final design.view is shown below.
###cd to Technology Library Path###
cd /home/du.566/cadence/GPDK45/
###Create Constraint from SDC File###
create_constraint_mode -name ALUConstraint -sdc_files [list synthesis/innovus/genus_outputs/ALUREG8bit.sdc]
###Create RC Corner from QX Techfile###
create_rc_corner -name rc_typical -qx_tech_file gsclib045_all_v4.4/gsclib045_tech/qrc/qx/gpdk045.tch
###Create Library Set for Each Corner###
create_library_set -name Slowlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v0_basicCells.lib}
create_library_set -name Fastlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v0_basicCells.lib}
create_library_set -name Slowlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v2_basicCells.lib}
create_library_set -name Fastlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v2_basicCells.lib}
###Create Delay Corner for Each Library Set and RC Corner###
create_delay_corner -name DCSlow -library_set {Slowlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCFast -library_set {Fastlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCSlow1v2 -library_set {Slowlib1v2} -rc_corner {rc_typical}
create_delay_corner -name DCFast1v2 -library_set {Fastlib1v2} -rc_corner {rc_typical}
###Create Analysis View for Each Constraint and Delay Corner###
create_analysis_view -name setup -constraint_mode ALUConstraint -delay_corner {DCSlow}
create_analysis_view -name hold-constraint_mode ALUConstraint -delay_corner {DCFast}
create_analysis_view -name setup1v2 -constraint_mode ALUConstraint -delay_corner {DCSlow1v2}
create_analysis_view -name hold1v2 -constraint_mode ALUConstraint -delay_corner {DCFast1v2}
###Set Analysis Views for Setup and Hold
set_analysis_view -setup {setup setup1v2] -hold {hold hold1v2}
Main Run
The design will now be placed and routed through another script.
Create a script in the Innovus folder named design.tcl and edit it.
Set the process node. This will be used for optimization purposes by Innovus during later stages.
setDesignMode -process 45
Set the netlisttype to verilog and the path to the netlist output by Genus. Remember to change the path your Cadence folder path - typically by replacing name.# with your OSU ID.
set init_design_netlisttype { Verilog }
set init_verilog { /home/<name.#>/cadence/GPDK45/synthesis/innovus/genus_outputs/ALUREG8bit.v }
Set the technology, cell abstract information and the MMMC view created earlier.
set init_oa_ref_lib { gsclib045 giolib045 gsclib045_tech }
set init_abstract_view { abstract }
set init_layout_view { layout }
set init_oa_default_rule { LEFDefaultRouteSpec }
set init_mmmc_file { /home/<name.#>/cadence/GPDK45/synthesis/innovus/ALU.view }
The oa_ref_libs are the standard cell libraries referenced inside the cds.lib in your Virtuoso directory.
The oa_default_rule chooses the DRC information within the tech LEF (.tlef) attached to the technology library.
The mmmc_file contains all timing information.
Set the power and ground net names for this design.
set init_pwr_net { VDD! }
set init_gnd_net { VSS! }
Tell Innovus to autogenerate vias rather than pick from the library, and initialize the design.
setGenerateViaMode -auto true init_design
Specify the floorPlan dimensions of the design.
floorPlan -site CoreSite -r 1 0.9 1.0 1.0 1.0 1.0
The -site option is mandatory, and creates a core row site. The -r option allows you to specify the ratio, and the following numbers specify aspectRatio, rowDensity, marginLeft, marginBottom, marginRight marginTop.
Connect the global power nets to the standard cell power and ground pins in schematic.
globalNetConnect VDD! -pin VDD -type pgpin globalNetConnect VSS! -pin VSS -type pgpin
If you don't know what the name of the standard cell power and ground pins are, open up the layout and find them. They may not be the same as in schematic. If you don't specify the correct pin names, Innovus will not find them, and will not connect your global power nets to your standard cells.
Route the power grid.
addStripe -nets { VDD! VSS! } -layer Metal11 -direction horizontal -width 1.8 -spacing 4 -set_to_set_distance 10
addStripe -nets { VDD! VSS! } -layer Metal10 -direction vertical -width 1.8 -spacing 4 -set_to_set_distance 10
sroute
addStripe adds the power grid with the specified horizontal and vertical metals.-width defines how wide the metals are in μm.-spacing defines the space between VDD and VSS stripes in μm.-set_to_set_distance defines the space between each VDD stripe or VSS stripe in μm.
The metals selected for each direction should conform with HVH or VHV.
Place design with auto pin placement.
setPlaceMode -place_global_place_io_pins true
place_design
Configure CCOpt to do Clock Tree Synthesis.
set_ccopt_property use_inverters true set_ccopt_property target_skew 116ps set_ccopt_property target_max_trans 150ps #setOptMode -usefulSkew false ccopt_design
CCOpt (Clock Concurrent Optimization) does optimization concurrently with clock tree synthesis, and running this command will generate a clock tree as well as reduce total negative slack (TNS).
A part of this optimization is useful skew, where the optimizer performs time borrowing between sequential cells to optimize for slack. If later on you see extremely high skew in your clock tree, use setOptMode -usefulSkew false, and check that your design is constrained realistically, and that you do not have multiple nanoseconds of negative slack.
Add filler cells.
addFiller -cell FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64 -prefix FILL -fitGap
addFiller -cell DECAP2 DECAP3 DECAP4 DECAP5 DECAP6 DECAP7 DECAP8 DECAP9 DECAP10 -prefix DECAP -fitGap
You should specify all available fill cells to this command so that it can select the appropriate ones to meet 100% core density.
Route the design.
routeDesign
Report timing for timing aware metal fill, and add the metal fill.
report_timing
addMetalFill -timingAware sta
If you want to connect the fill nets to power, supply the -nets { VDD! VSS! } option.
The final script is shown below.
setDesignMode -process 45
set init_design_netlisttype { Verilog }
set init_verilog { /home/<name.#>/cadence/GPDK45/synthesis/innovus/genus_outputs/ALUREG8bit.v }
set init_oa_ref_lib { gsclib045 giolib045 gsclib045_tech }
set init_abstract_view { abstract }
set init_layout_view { layout }
set init_oa_default_rule { LEFDefaultRouteSpec }
set init_mmmc_file { /home/<name.#>/cadence/GPDK45/synthesis/innovus/ALU.view }
set init_pwr_net { VDD! }
set init_gnd_net { VSS! }
setGenerateViaMode -auto true
init_design
floorPlan -site CoreSite -r 1 0.9 1.0 1.0 1.0 1.0
globalNetConnect VDD! -pin VDD -type pgpin
globalNetConnect VSS! -pin VSS -type pgpin
addStripe -nets { VDD! VSS! } -layer Metal11 -direction horizontal -width 1.8 -spacing 4 -set_to_set_distance 10
addStripe -nets { VDD! VSS! } -layer Metal10 -direction vertical -width 1.8 -spacing 4 -set_to_set_distance 10
sroute
setPlaceMode -place_global_place_io_pins true
place_design
set_ccopt_property use_inverters true
set_ccopt_property target_skew 116ps
set_ccopt_property target_max_trans 150ps
ccopt_design
addFiller -cell FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64 -prefix FILL -fitGap
addFiller -cell DECAP2 DECAP3 DECAP4 DECAP5 DECAP6 DECAP7 DECAP8 DECAP9 DECAP10 -prefix DECAP -fitGap
routeDesign
report_timing
addMetalFill -timingAware sta
GUI
At this point, the design is fully routed. Open the GUI by typing win in the Innovus terminal when the script finishes. This will bring up the main Innovus window.
You can also view the clock tree by typing ctd_win in the Innovus terminal. This will bring up the clock tree debugger.
Timing
To report the timing, use the report_timing command.
By default, this will report the setup time of the single worst path.
innovus #> report_timing
###############################################################
# Generated by: Cadence Innovus 18.12-s106_1
# OS: Linux x86_64(Host ID ece-d01181524s.coeit.osu.edu)
# Generated on: Thu Feb 27 09:34:14 2020
# Design: ALUREG8bit
# Command: report_timing > timing.log
###############################################################
Path 1: MET Setup Check with Pin OREGZ_Q_reg[0]/CK
Endpoint: OREGZ_Q_reg[0]/D (^) checked with leading edge of 'clk1'
Beginpoint: IREG1_Q_reg[1]/Q (^) triggered by leading edge of 'clk1'
Path Groups: {clk1}
Analysis View: setup
Other End Arrival Time 0.011
- Setup 0.102
+ Phase Shift 3.500
= Required Time 3.409
- Arrival Time 3.384
= Slack Time 0.025
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.010
= Beginpoint Arrival Time 0.010
+----------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|---------------------------+--------------+----------+-------+---------+----------|
| IREG1_Q_reg[1] | CK ^ | | | 0.010 | 0.035 |
| IREG1_Q_reg[1] | CK ^ -> Q ^ | DFFQX2 | 0.277 | 0.287 | 0.312 |
| ALU/mul_35_23_g1541__8780 | B ^ -> Y ^ | AND2X1 | 0.178 | 0.465 | 0.490 |
| ALU/mul_35_23_g1454__3772 | A ^ -> S v | ADDFX1 | 0.313 | 0.778 | 0.803 |
| ALU/mul_35_23_g1441__7114 | CI v -> S ^ | ADDFHXL | 0.259 | 1.037 | 1.062 |
| ALU/mul_35_23_g1427__1474 | CI ^ -> CO ^ | ADDFX1 | 0.189 | 1.226 | 1.251 |
| ALU/mul_35_23_g1423__9906 | CI ^ -> CO ^ | ADDFX1 | 0.192 | 1.417 | 1.442 |
| ALU/mul_35_23_g1420__1840 | CI ^ -> CO ^ | ADDFX1 | 0.194 | 1.611 | 1.636 |
| ALU/mul_35_23_g1419__7344 | CI ^ -> CO ^ | ADDFX1 | 0.202 | 1.814 | 1.838 |
| ALU/FE_RC_17_0 | B ^ -> Y v | NAND2BX1 | 0.077 | 1.890 | 1.915 |
| ALU/FE_RC_16_0 | B v -> Y ^ | NAND2X1 | 0.055 | 1.946 | 1.970 |
| ALU/mul_35_23_g1417__2703 | CI ^ -> CO ^ | ADDFX1 | 0.197 | 2.142 | 2.167 |
| ALU/FE_RC_41_0 | B ^ -> Y v | NAND2BX2 | 0.071 | 2.214 | 2.238 |
| ALU/FE_RC_40_0 | B v -> Y ^ | NAND2X2 | 0.056 | 2.269 | 2.294 |
| ALU/FE_RC_32_0 | B ^ -> Y v | NAND2BX2 | 0.063 | 2.332 | 2.357 |
| ALU/FE_RC_31_0 | B v -> Y ^ | NAND2X1 | 0.051 | 2.384 | 2.409 |
| ALU/mul_35_23_g1414__5266 | CI ^ -> S v | ADDFX1 | 0.283 | 2.666 | 2.691 |
| ALU/g6292__7675 | C v -> Y v | OR4XL | 0.247 | 2.914 | 2.939 |
| ALU/FE_RC_5_0 | A v -> Y ^ | INVX1 | 0.047 | 2.961 | 2.986 |
| ALU/FE_RC_4_0 | B ^ -> Y v | NAND2X2 | 0.061 | 3.022 | 3.047 |
| ALU/FE_RC_3_0 | B v -> Y ^ | NOR3X2 | 0.125 | 3.147 | 3.172 |
| ALU/g6254__4296 | B1 ^ -> Y v | AOI221X2 | 0.147 | 3.294 | 3.319 |
| ALU/FE_RC_0_0 | B v -> Y ^ | NAND2X2 | 0.090 | 3.384 | 3.409 |
| OREGZ_Q_reg[0] | D ^ | DFFHQX2 | 0.000 | 3.384 | 3.409 |
+----------------------------------------------------------------------------------+
To do Hold analysis, use setAnalysisMode. This will report the single worst case hold time as well.
innovus #> setAnalysisMode -checkType Hold
innovus #> report_timing
###############################################################
# Generated by: Cadence Innovus 18.12-s106_1
# OS: Linux x86_64(Host ID ece-d01181524s.coeit.osu.edu)
# Generated on: Thu Feb 27 09:37:33 2020
# Design: ALUREG8bit
# Command: report_timing > hold.log
###############################################################
Path 1: MET Early External Delay Assertion
Endpoint: Result[4] (^) checked with leading edge of 'clk1'
Beginpoint: OREG_Q_reg[4]/Q (^) triggered by leading edge of 'clk1'
Path Groups: {clk1}
Analysis View: hold1v2
Other End Arrival Time 0.000
- External Delay 0.010
+ Phase Shift 0.000
= Required Time -0.010
Arrival Time 0.056
Slack Time 0.066
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.003
= Beginpoint Arrival Time 0.003
+-------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|---------------+-------------+--------+-------+---------+----------|
| OREG_Q_reg[4] | CK ^ | | | 0.003 | -0.063 |
| OREG_Q_reg[4] | CK ^ -> Q ^ | DFFQX2 | 0.053 | 0.055 | -0.010 |
| | Result[4] ^ | | 0.000 | 0.056 | -0.010 |
+-------------------------------------------------------------------+
Design Checks
Innovus can check for connectivity, drc, metal density, and process antenna. If you pass all of these, LVS and DRC should be (almost) clean.
verifyConnectivity -noAntenna -report design_conn.rpt
verify_drc -report design_drc.rpt
verifyMetalDensity -report design_density.rpt
verifyProcessAntenna -report design_antenna.rpt
These will generate reports that you can view. If you see errors with connectivity or drc, use the zoomTo x y -r radius command to zoom to coordinates and pinpoint the exact cause of the issue.
Saving
After you have passed all checks as well as timing, you can save the design to Virtuoso. Open the GUI, and go to File -> Save, or press F2. From here, you can select which library and cellview to save it as.
To save the SDF file, use write_sdf with the selected view.
write_sdf ALU.sdf
You can now export this to Incisive again to do postlayout simulations.