You are here

Tawfiq Musah

  • Assistant Professor, Electrical & Computer Engr.
  • 2015 Neil Ave
    Columbus, OH 43210

About

Office: 316 Dreese

Phone: 614-292-0391 

Website: http://u.osu.edu/musah.3


Tawfiq Musah received the B.S. degree from Columbia University, New York, NY, USA, in 2005 and the Ph.D. degree from Oregon State University, Corvallis, OR, USA, in 2010, both in electrical engineering.
Dr. Musah is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The Ohio State University, Columbus, OH.  From 2010 to 2018, he worked at the Signaling Research Lab at Intel Corporation, Hillsboro, OR, USA, on circuits and systems to enable Intel’s next generation chip-to-chip electrical and optical links. Before joining Intel, he interned at Texas Instruments (TI) designing a hardware sensor in early 2010 and Intel Labs working on micro-power ADC in 2006 and 2007.
His research interests include low-power equalization techniques for next-generation electrical and optical I/O links, multi-GS/s ADCs and high-level circuit modeling and verification.
He is a senior member of IEEE. and a recipient of several awards, including the Intel Labs Divisional Recognition Award in 2014 and 2017 and Intel Labs Academy Award for Excellence in Bringing New Experiences or Technical Innovation to Market in 2015.


Journal Papers 


[1] T. Musah, J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, “A 4-32Gb/s Bidirectional Link with 3-tap FFE/6-tap DFE and Collaborative CDR in 22nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 12, pp. 3079-3090, Dec. 2014.
[2] T. Musah and U. Moon, “Correlated level shifting integrator with reduced sensitivity to amplifier gain,”
Electron. Lett. (EL), vol. 47, no. 2, pp. 91-92, Jan. 29, 2011.
[3] Y. Hu, N, Maghari, T. Musah, and U. Moon, “Time-interleaved noise-shaping integrating quantisers,”
Electron. Lett. (EL), vol. 46, no. 11, pp. 757-758, May 27, 2010.
[3] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, “Design of a 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC,” IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 719-730, Apr. 2010.
[4] T. Musah and U. Moon, “Correlated level shifting technique with cross-coupled gain-enhancement
capacitors,” Electron. Lett. (EL), vol. 45, no. 13, pp. 672-674, Jun. 18, 2009.
[5] T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon, “Parallel correlated double sampling technique for pipelined analogue-to-digital converters,” Electron. Lett. (EL), vol. 43, no. 23, Nov. 8, 2007.
Conference Papers
[1] J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, T. Musah, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, “A 205mW 32Gb/s 3-Tap FFE/6-Tap DFE Bi-directional Serial Link in 22nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 440-441, Feb. 2014.
[2] T.-C. Hsueh, G. Balamurugan, J. Jaussi, S. Hyvonen, J. Kennedy, G. Keskin, T. Musah, S. Shekhar, R. Inti, S. Sen, M. Mansuri, C. Roberts, B. Casper, “A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 444-445, Feb. 2014.
[3] B. Hershberg, T. Musah, S. Weaver, and U. Moon, “The effect of correlated level shifting on noise performance in switched capacitor circuits,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 942-945, May 2012.
[4] B.R. Gregoire, T. Musah, N. Maghari, S. Weaver, and U. Moon, “A 30% beyond Vdd signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp,” IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 345-348, Nov. 2011.
[5] O. Rajaee, Y. Hu, M. Gande, T. Musah, and U. Moon, “An interstage correlated double sampling technique for switched-capacitor gain stages,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1252-1255, May 2010.
[6] T. Musah and U. Moon, “Pseudo-differential zero-crossing-based circuits with differential
error suppression,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1731-1734, May 2010.
[7] T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon, “A 630uW zero-crossing-based delta-sigma ADC using switched-resistor current sources in 45nm CMOS,” IEEE Custom Int. Circuits Conf. (CICC), pp. 1-4, Sep. 2009.
[8] O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, and U. Moon, “A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC,” IEEE Symp. VLSI Circuits (VLSI), pp. 74-75, Jun. 2009.
[9] S. Chatterjee, T. Musah, Y. Tsividis, and P. Kinget, “Weak inversion MOS varactors for 0.5 V analog integrated filters,” IEEE Symp. VLSI Circuits (VLSI), Jun. 2005, pp. 272-275.
Patents
[1] J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, T.-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements,” US Patent Number: 9589615, Mar. 2017.
[2] H. Venkatram, S. Hyvonen, T. Musah, and B. Casper, “High speed receiver with one-hot decision feedback equalizer,” US Patent Number: 9537682, Jan. 2017.
[3] T. Musah, G. Keskin, G. Balamurugan, J. E. Jaussi, and B. Casper, “Wireline receiver circuitry having collaborative timing recovery,” US Patent Number: 9374250, Jun. 2016.



 

 

Journal Articles

2014

  • Musah, T.; Jaussi, J.; Balamurugan, G.; Hyvonen, S. et al., 2014, "A 4-32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS." IEEE Journal of Solid-State Circuits 49, no. 12, 3079-3090 - 3079-3090.

2011

  • Musah, T.; Moon, U.K., 2011, "Correlated level shifting integrator with reduced sensitivity to amplifier gain." Electronics Letters 47, no. 2, 91-92 - 91-92.

2010

  • Hu, Y.; Maghari, N.; Musah, T.; Moon, U., 2010, "Time-interleaved noise-shaping integrating quantisers." Electronics Letters 46, no. 11, 757-758 - 757-758.
  • Rajaee, O.; Musah, T.; Maghari, N.; Takeuchi, S. et al., 2010, "Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC." IEEE Journal of Solid-State Circuits 45, no. 4, 719-730 - 719-730.

2009

  • Musah, T.; Moon, U.K., 2009, "Correlated level shifting technique with cross-coupled gain-enhancement capacitors." Electronics Letters 45, no. 13, 672-674 - 672-674.

2007

  • Musah, T.; Gregoire, B.R.; Naviasky, E.; Moon, U.K., 2007, "Parallel correlated double sampling technique for pipelined analogue-to-digital converters." Electronics Letters 43, no. 23, 1260-1261 - 1260-1261.

Papers in Proceedings

2014

  • Hsueh, T-C.; Balamurugan, G.; Jaussi, J.; Hyvonen, S. et al. "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS." in 1st IEEE International Solid-State Circuits Conference (ISSCC). (1 2014).
  • Jaussi, J.; Balamurugan, G.; Hyvonen, S.; Hsueh, T-C. et al. "A 205mW 32Gb/s 3-Tap FFE/6-Tap DFE Bidirectional Serial Link in 22nm CMOS." in 1st IEEE International Solid-State Circuits Conference (ISSCC). (1 2014).

2012

  • Hershberg, B.; Musah, T.; Weaver, S.; Moon, U-K. "The Effect of Correlated Level Shifting on Noise Performance in Switched Capacitor Circuits." in IEEE International Symposium on Circuits and Systems. (1 2012).

2011

  • Gregoire, B.R.; Musah, T.; Maghari, N.; Weaver, S. et al. "A 30% beyond V DD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp." (12 2011).

2010

  • Rajaee, O.; Hu, Y.; Gande, M.; Musah, T. et al. "An interstage correlated double sampling technique for switched-capacitor gain stages." (8 2010).
  • Musah, T.; Moon, U-K. "Pseudo-Differential Zero-Crossing-Based Circuit with Differential Error Suppression." in International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010). (1 2010).

2009

  • Rajaee, O.; Musah, T.; Takeuchi, S.; Aniya, M. et al. "A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC." (11 2009).
  • Musah, T.; Kwon, S.; Lakdawala, H.; Soumyanath, K. et al. "A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS." (12 2009).

2005

  • Chatterjee, S.; Musah, T.; Tsividis, Y.; Kinget, P. "Weak inversion MOS varactors for 0.5 v analog integrated filters." (12 2005).

Patents

  • "Wireline receiver circuitry having collaborative timing recovery." Patent number: 9374250
  • "High speed receiver with one-hot decision feedback equalizer." Patent number: 9537682
  • "Digitally trimmable integrated resistors including resistive memory elements." Patent number: 9589615