Guest Speaker: Pankaj Mehra

Date / Time: Monday, April 3, 2023; 10:00 am Location: 480 Dreese Labs

Talk Title: Bits, Cores, and Fabrics: Infrastructure ingredients for recipes in Computational Storage, Near Data Processing, and Memory as a Service

Talk Abstract: 

Driven by inexorable advances toward Contextual Intelligence, technology infrastructures for data, computation, and communication have evolved over four decades through three independent streams of advances in architecture. Concentrated in 100s of 100,000-server data centers where 1,000s of containers launch every second, these technologies absorb 1,000s of hours of video every minute, accumulate exabytes of data in lakes, learn patterns in it by applying 10s of zettaflops of deep compute, and connect the dots on petabytes of in-memory graph data from 100s of  sources in real time. Economic forces, walls of power and memory, recently exposed inefficiencies, and the opportunity to embed logic and connectivity everywhere, and what some call the Moore's Law of Packaging, have now put us on the cusp of an unprecedented wave  of semiconductor integration of these independent streams, enabling hardware disaggregation of and software re-aggregation of servers in the data center. We will look philosophically and practically at these trends, and the resulting design challenges and opportunities through the lens of smart SSDs, disaggregated memory nodes, and the possibility of delivering and consuming memory as a service. The talk ends with a vision of the data center of 2030 and the blueprint for an industry-aligned research roadmap for academia.

Bio:

Pankaj Mehra is President and CEO of Elephance Memory and Adjunct Associate Professor of Computer Science at University of California, Santa Cruz. He actively advises Memory industry companies. An author of some of the earliest work showing the classic 'S' curve of machine learning applied to problems in computer systems, Pankaj Mehra is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents. His international experience includes roles in academia, industry, and government leading labs, startups, incubations, and products. Pankaj's systems have held TPC-C and Terabyte Sort performance records, and his work has been recognized by Awards from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj chaired the Management working group in InfiniBand Trade Association.