VLSIARC
VLSI System Architecture Lab
Link List
Prof. Zhang is looking for highly-motivated students to join her group. RA positions are available to start in Fall 2024. Interested students may send me CV and transcripts in PDF.
Xinmiao Zhang received her Ph.D. degree in Electrical Engineering from the University of Minnesota, Twin Cities. She is currently a Professor at the Ohio State University and was a Timothy E. and Allison L. Schroeder Assistant Professor 2005-2010 and Associate Professor 2010-2013 at Case Western Reserve University. Between her academic careers, she was a Senior Technologist at Western Digital/ SanDisk 2013-2017. She is also a member of the core faculty of the Translational Data Analytics Institute of the Ohio State University. She held visiting positions at the University of Washington, Seattle, 2011-2013 and Qualcomm in 2008.
Prof. Zhang’s research spans the areas of VLSI architecture design, digital storage and communications, hardware security, cryptography, and signal processing. She developed many VLSI architectures to improve the hardware efficiency of state-of-the-art error-correcting coding and cryptographic schemes, including hard- and soft-decision BCH and Reed-Solomon codes as well as their variations, binary and non-binary low-density parity-check codes, and the Advanced Encryption Standard (AES). Her recent work on generalized integrated interleaved codes enabled Terabyte/s decoding with excellent error-correcting performance. She authored the book “VLSI Architectures for Modern Error-Correcting Codes” (CRC 2015) and her work on the Advanced Encryption Standard (AES) received more than 1000 citations. Her current research focuses on VLSI architecture design for error and erasure-correcting codes enabling hyper-speed large-scale memory/distributed storage, hardware security, homomorphic encryption, post-quantum cryptography, and machine learning.
Prof. Zhang is a recipient of NSF CAREER Award 2009, the College of Engineering Lumley Research Award at The Ohio State University 2022, the Best Paper Award at ACM Great Lakes Symposium on VLSI 2004, and Best Paper Award at International SanDisk Technology Conference 2016.
Prof. Zhang was elected the Vice President-Technical Activities of the IEEE Circuits and Systems Society (CASS) for the 2022-2023 term and the Chair of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society for the 2021-2022 term. She also served on the Board of Governors of CASS for the 2019-2021 term and was a Vice-Chair of DSTC 2017-2020. She was the Chair of the Seasonal Schools Program of the IEEE Signal Processing Society 2013-2015. She has been a member of the CASS Circuits and Systems for Communications (CASCOM) Technical Committee since 2007 and VLSI Systems and Applications (VSA) Technical Committee since 2006. She was also a member of the Design and Implementation of Signal Processing Systems (DISPS) Technical Committee of the IEEE Signal Processing Society 2008-2014. Prof. Zhang has served on the organization and technical program committees of many conferences, such as the IEEE International Symposium on Circuits and Systems (ISCAS), IEEE International Conference on Communications (ICC), IEEE Workshop on Signal Processing Systems (SiPS), IEEE Global Communications Conference (GLOBECOM), Non-Volatile Memories Workshop, and ACM Great Lakes Symposium on VLSI (GLSVLSI). She has been an associate editor for the IEEE Transactions on Circuits and Systems-I 2010-2019 and IEEE Open Journal of Circuits and Systems since 2019. She was a recipient of the Best Associate Editor Award in 2013 and 2021.
Research
Research Interest:
VLSI architecture design, digital storage and communications, hardware security, cryptography, and signal processing; translating theoretical advancements to highly efficient practical VLSI implementations through integrated algorithmic and architectural optimizations.
Current Research Topics:
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VLSI architecture design for error and erasure-correcting coding enabling hyper-speed and large-scale digital storage
Memory and storage systems are the backbone of big data analytics, cloud computing, data virtualization, and many other pervasive applications. Error-correcting codes (ECCs) are essential to the reliability of memories, and largely affect the performance and cost of the overall storage system. To enable data access and analytics with unprecedented hyper speed, it is necessary to incorporate the specifics of the memories and applications in the ECC and VLSI architecture design. Additionally, to facilitate the continued scaling of distributed storage, the key is to develop high-performance, yet practical locally recoverable erasure codes and their low-complexity implementations that substantially reduce the latency and network bandwidth overhead associated with recovering from unavailable data and/or failures.
- Hardware security
With the advancements of reverse engineering tools, it is becoming easier to steal IPs from IC chips and make illegal copies. This brings billions of dollars lose to the IP owners. One of the most effective methodologies for preventing chip counterfeiting is logic locking, which inserts key-controlled blocks and corrupts the circuit output when an incorrect key is used. Nevertheless, various attacks have also been developed to compromise logic-locking schemes. It is essential to develop advanced and low-overhead schemes that are better at resisting all possible attacks. Additionally, fault-tolerant or self-correcting circuits, such as those implementing machine learning and approximate computing, pose new challenges for logic locking. Algorithmic features must be integrated in order to effectively corrupt the output when the wrong key is utilized.
- VLSI architecture design for post-quantum cryptography
Much research has been carried out on quantum computers in recent years. In the existence of large-scale quantum computers, many difficult mathematical problems, such as large number factorization and discrete logarithm, will become solvable in polynomial time. Current public-key ciphers are based on these math problems and will be broken. NIST calls for competitions to establish new post-quantum cryptography standard. Evaluations are given to not only the achievable security level, but also the implementation complexity on both hardware and software. Optimized hardware implementation architectures and data flows should be developed for the candidates before the complexity comparisons are carried out. Meanwhile, algorithmic and architectural modifications resistant to side-channel attacks need to be studied.
- Hardware accelerator design for homomorphic encryption
Unlike the schemes in current cryptography standards, such as AES, RSA, and elliptic curve cryptography, homomorphic encryption is a new technique that allows compute to be directly carried out on ciphertexts. It is the key enabler for privacy-preserving cloud computing. On the other hand, its high-speed hardware implementation faces many challenges. To avoid the expensive bootstrapping process, polynomials with thousands of coefficients, each of which has hundreds of bits, are utilized and modular computations are carried out. To increase the speed of the operations over ciphertexts to practical level, it is essential to develop hardware accelerators that not only have optimized individual computation units but also exploit algorithmic specifics to reduce the amount of calculations needed.
- Error-correcting codes for high-density integration and heterogenous interconnects
Compared to the traditional triple redundancy for tolerating defects and errors in circuits, ECCs have much lower overheads and are essential to realizing high-density integration. Additionally, heterogeneous interconnects that utilize wireless or optical links solve the routing congestion problem in ultra-scale circuits. Carefully designed ECCs can dramatically reduce the signal transmission power. The ECC design achieving these goals faces many new challenges. The decoder must not involve any iterative computations and should have very short data path. Besides, ECCs should only be added to proper signals in the circuit to minimize the overheads while correcting the errors that would corrupt the output. The code and en/decoder implementation should be jointly designed to address these issues.
Past Research Topics:
- Non-binary & binary low-density parity-check (LDPC) codes
- Algebraic soft-decision & hard-decision Reed-Solomon (RS) and BCH codes
- Advanced Encryption Standard (AES) algorithm
- Finite field arithmetic
- RSA public-key cipher
Sponsors:
Publications
Books:
2. X. Zhang, VLSI Architectures for Modern Error Correcting Codes, CRC Press, Jul. 2015.
1. N. Sklavos and X. Zhang, Ed., Wireless Security & Cryptography: Specifications and Implementations, CRC Press, Mar. 2007.
Book Chapter:
1. X. Zhang, "Efficient VLSI Architectures for the AES Algorithm," in N. Sklavos and X. Zhang ed. Wireless Security and Cryptography: Specifications and Implementations, CRC Press, Mar. 2007.
Journal Publications:
57. S. Akherati and X. Zhang, “Low-complexity ciphertext multiplication for CKKS homomorphic encryption,” IEEE Trans. on Circuits and Systems-II, 2023.
56. J. Cai and X. Zhang, “Low-complexity parallel Min-sum medium-density parity-check decoder for McEliece cryptosystem,” IEEE Transactions on Circuits and Systems-I, 2023.
55. Y. J. Tang and X. Zhang, “Generalized integrated interleaved codes for high-density DRAMs,” IEEE Transactions on Circuits and Systems-II, 2023.
54. Y. J. Tang and X. Zhang, “Fast and low-complexity soft-decision generalized integrated interleaved decoder,” IEEE Journal on Selected Areas in Information Theory, 2023.
53. J. Zhou and X. Zhang, “Joint protection scheme for deep neural network hardware accelerators and models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
52. Z. Xie and X. Zhang, “Sparsity-aware medium-density parity-check decoder for McEliece cryptosystems,” IEEE Transactions on Circuits and Systems-II, 2023.
51. W. Tan, A. Wang, X. Zhang, Y. Lao, and K. K. Parhi, “High-speed VLSI architectures for modular polynomial multiplication via fast filtering and applications to lattice-based cryptography,” IEEE Transactions on Computers, 2023.
50. J. Zhou and X. Zhang, “Algorithmic obfuscation for LDPC decoders,” IEEE Transactions on Computer-Aided Design, vol. 42, no. 2, pp. 371-383, Feb. 2023.
49. Z. Huai, J. Zhou, and X. Zhang, “Efficient hardware implementation architectures for long integer modular multiplication over general Solinas prime,” Springer Journal of Signal Processing Systems, vol. 94, pp. 1067-1082, Aug. 2022.
48. Z. Xie, Y. J. Tang, and X. Zhang, “Low-latency nested decoding for short generalized integrated interleaved BCH codes,” IEEE Trans. on VLSI Systems, 2022.
47. X. Zhang, Z. Huai, and K. K. Parhi, “Polynomial multiplication architecture with integrated modular reduction for R-LWE cryptosystems,” Springer Journal of Signal Processing Systems, vol. 94, pp. 799-809, Apr. 2022.
46. O. Ferraz, S. Subramaniyan, R. Chinthalaa, J. Andrade, J. R. Cavallaro, S. K. Nandy, V. Silva, X. Zhang, M. Purnaprajna, and G. Falcao, “A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA and GPU architectures,” IEEE Communications Surveys and Tutorials, 2021.
45. Y. J. Tang and X. Zhang, “Low-complexity resource-shareable parallel generalized integrated interleaved encoder,” IEEE Trans. on Circuits and Systems-I, 2021.
44. Z. Xie and X. Zhang, “Efficient sub-codeword key equation solver for generalized integrated interleaved BCH decoder,” IEEE Transactions on Circuits and Systems-II, 2021.
43. Z. Xie and X. Zhang, “Miscorrection mitigation for generalized integrated interleaved BCH codes,” IEEE Communications Letters, 2021.
42. Y. J. Tang and X. Zhang, “Fast en/decoding of Reed-Solomon codes for failure recovery,” IEEE Trans. on Computers, 2021.
41. J. Zhou and X. Zhang, “Generalized SAT-attack-resistant logic locking,” IEEE Transactions on Information Forensics and Security, vol. 16, pp. 2581-2592, 2021.
40. Z. Xie and X. Zhang, “Fast nested key equation solvers for generalized integrated interleaved decoder,” IEEE Trans. Circuits and Syst.-I, vol. 68, no. 1, pp. 483-495, Jan. 2021.
39. X. Zhang, “VLSI architectures for Reed-Solomon codes: classic, nested, coupled, and beyond,” IEEE Open Journal of Circuits and Syst., vol. 1, pp. 157-169, 2020.
38. Z. Xie and X. Zhang, "Reduced-complexity key equation solvers for generalized integrated interleaved BCH decoders," IEEE Trans. Circuits and Syst.-I, vol. 67, no. 12, pp. 5520-5529, 2020.
37. Z. Xie and X. Zhang, "Scaled nested key equation solver for generalized integrated interleaved decoder," IEEE Trans. Circuits and Syst.-II, vol. 67, no. 11, pp. 2457-2461, 2020.
36. X. Zhang and Z. Xie, "Efficient VLSI architectures for coupled-layered regenerating codes," IEEE Trans. Circuits and Syst.-II, vol. 67, no. 10, pp. 1869-1873, Oct. 2020.
35. X. Zhang and Z. Xie, "Relaxing the constraints on locally recoverable erasure codes by finite field element variation," IEEE Communications Letters, vol. 23, no. 10, pp. 1680-1683, Oct. 2019.
34. X. Zhang and Z. Xie, “Efficient architectures for generalized integrated interleaved decoder," IEEE Trans. Circuits and Syst.-I, vol. 66, no. 10, pp. 4018-4031, Oct. 2019..
33. X. Zhang and Y. Lao, “On the construction of composite finite fields for hardware obfuscation," IEEE Trans. on Computers, vol. 68, no. 9, pp. 1353-1364, 2019.
32. X. Zhang, “A low-power parallel architecture for linear feedback shift registers," IEEE Trans. Circuits and Syst.-II, vol. 66, no. 3, pp. 412-416, Mar. 2019.
31. X. Zhang, “Generalized three-layer integrated interleaved codes,” IEEE Communications Letters, vol. 22, no. 3, pp. 442-445, Mar. 2018.
30. X. Zhang, “Modified generalized integrated interleaved codes for local erasure recovery,” IEEE Communications Letters, vol. 21(6), pp 1241-1244, Jun. 2017.
29. X. Zhang and Y. Tai, “Low-complexity transformed encoder architectures for quasi-cyclic non-binary LDPC codes over subfields,” IEEE Trans. on VLSI Systems, vol. 25(4), pp. 1342-1351, 2017.
28. X. Zhang, S. Sprouse and I. Ilani, “A flexible and low-complexity local erasure recovery scheme,” IEEE Communications Letters, vol. 50(11), pp. 2129 - 2132, Nov. 2016.
27. X. Zhang, “Low-complexity Min-max non-binary LDPC decoders,” Journal of Communications, vol. 10 (11), pp. 836-842, Nov. 2015.
26. F. Cai, X. Zhang, D. Declercq, S. K. Planjery and B. Vasic, “Finite alphabet iterative decoders for LDPC codes: optimization, architecture and analysis,” IEEE Trans. on Circuits and Systems-I, vol. 61(5), pp. 1366-1375, May 2014.
25. F. Cai and X. Zhang, “Relaxed min-max decoder architectures for non-binary LDPC code,” IEEE Trans. on VLSI Systems, vol. 21(11), pp. 2010-2023, Nov. 2013.
24. F. Cai and X. Zhang, “Efficient check node processing architectures for non-binary LDPC decoding using power representation,” Springer Journal of Signal Processing Systems, vol. 76(2), pp. 211-222, Nov. 2013.
23. X. Zhang, “An efficient interpolation-based Chase BCH decoder,” IEEE Trans. on Circuits and Systems-II, vol. 60(4), pp. 212-216, Apr. 2013.
22. X. Zhang and Y. Zheng, “Generalized backward interpolation for algebraic soft-decision decoding of Reed-Solomon codes,” IEEE Trans. on Communications, vol. 61(1), pp. 13-23, Jan. 2013.
21. X. Zhang, F. Cai, and S. Lin, “Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes,” IEEE Trans. on VLSI Systems, vol. 20(11), pp. 1938-1950. Nov. 2012.
20. X. Zhang and Z. Wang, “A low-complexity three-error-correcting BCH decoder for optical transport network,” IEEE Trans. on Circuits and Systems-II, vol. 59(10), pp. 663-667, Oct. 2012.
19. X. Zhang, Y. Wu, J. Zhu, and Y. Zheng, “Novel polynomial selection and interpolation for low-complexity Chase algebraic soft-decision Reed-Solomon decoding,” IEEE Trans. on VLSI Systems, vol. 20(7), pp. 1318-1322, Jul. 2012.
18. X. Zhang and Y. Zheng, “Systematically re-encoded algebraic soft-decision Reed-Solomon decoder,” IEEE Trans. on Circuits and Systems-II, vol. 59(6), pp. 376-380, Jun. 2012.
17. X. Zhang, J. Zhu and W. Zhang, “Efficient re-encoder architectures for algebraic soft-decision Reed-Solomon decoding,” IEEE Trans. on Circuits and Systems-II, vol. 59(3), pp. 163-167, Mar. 2012.
16. J. Zhu and X. Zhang, “Efficient generalized minimum-distance decoders of Reed-Solomon codes,” Springer Journal of Signal Processing Systems, vol. 66(3), pp. 245-257, Mar. 2012.
15. X. Zhang, J. Zhu and W. Zhang, “Modified low-complexity Chase soft-decision decoder of Reed-Solomon codes,” Springer Journal of Signal Processing Systems, vol. 66(1), pp. 3-13, Jan. 2012.
14. X. Zhang and F. Cai, “Reduced-complexity decoder architecture for non-binary LDPC codes,” IEEE Trans. on VLSI Systems, vol. 19(7), pp. 1229-1238, Jul. 2011.
13. X. Zhang and F. Cai, “Efficient partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes,” IEEE Trans. on Circuits and Systems-I, vol. 58(2), pp. 402-414, Feb. 2011.
12. S. Paul, F. Cai, X. Zhang and S. Bhunia, “Reliability-driven ECC allocation for multiple bit error resilience in processor cache,” IEEE Trans. on Computers, vol. 60(1), pp. 20-34, Jan. 2011.
11. X. Zhang and J. Zhu, “Algebraic soft-decision decoder architectures for long Reed-Solomon codes,” IEEE Trans. on Circuits and Systems-II, vol. 57(10), pp. 787-792, Oct. 2010.
10. X. Zhang and J. Zhu, “High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding,” IEEE Trans. on Circuits and Systems-I, vol. 57(3), pp. 581-591, Mar. 2010.
9. J. Zhu, X. Zhang and Z. Wang, “Backward interpolation for algebraic soft-decision Reed-Solomon decoding,” IEEE Trans. on VLSI Systems, vol. 17(11), pp. 1602-1615, Nov. 2009.
8. J. Zhu and X. Zhang, “Efficient VLSI architecture for soft-decision decoding of Reed-Solomon codes,” IEEE Trans. on Circuits and Systems-I, vol. 55(10), pp. 3050-3062, Nov. 2008.
7. X. Zhang, “Further exploring the strength of prediction in the factorization of soft-decision Reed-Solomon decoding,” IEEE Trans. on VLSI Systems, vol. 15(7), pp. 811-820, Jul. 2007.
6. X. Zhang, “Reduced complexity interpolation architecture for soft-decision Reed-Solomon decoding,” IEEE Trans. on VLSI Systems, vol. 14(10), pp. 1156-1161, Oct. 2006.
5. X. Zhang and K. K. Parhi, “On the optimum constructions of composite field for the AES algorithm,” IEEE Trans. on Circuits and Systems-II, vol. 53(10), pp. 1153-1157, Oct. 2006.
4. X. Zhang and K. K. Parhi, “High-speed architectures for parallel long BCH encoders,” IEEE Trans. on VLSI Systems, vol. 13(7), pp. 872-877, Jul. 2005.
3. X. Zhang and K. K. Parhi, “Fast factorization architecture in soft-decision Reed-Solomon decoding,” IEEE Trans. on VLSI Systems, vol. 13(4), pp. 413-426, Apr. 2005.
2. X. Zhang and K. K. Parhi, “High-speed VLSI architectures for the AES algorithm,” IEEE Trans. on VLSI Systems, vol. 12(9), pp. 957-967, Sep. 2004.
1. X. Zhang and K. K. Parhi, “Implementation approaches for the Advanced Encryption Standard algorithm,” IEEE Circuits and Systems Magazine, vol. 2(4),pp. 24-46, Fourth Quarter 2002.
Conference Publications:
70. Y. J. Tang and X. Zhang, “Efficient reconfigurable Vandermonde matrix inverter for erasure-correcting generalized integrated interleaved decoding”, Proc. of IEEE Workshop on Signal Processing Systems, Nov. 2022.
69. Z. Xie and X. Zhang, “Improved miscorrection detection for generalized integrated interleaved BCH codes,” Proc. of IEEE International Conference on Communications, May 2022.
68. X. Zhang, “Efficient check node processing for Min-Max NB-LDPC decoding over lower-order finite fields,” Proc. of IEEE International Symposium on Circuits and Systems, May 2022.
67. J. Zhou, S. Elgendy, E. Y. Tawfik, and X. Zhang, “Low-complexity AES architectures resilient to power analysis attacks,” Proc. of IEEE International Symposium on Circuits and Systems, May 2022.
66. Z. Xie and X. Zhang, “Efficient nested key equation solver for short generalized integrated interleaved BCH codes, Proc. of IEEE International Symposium on Circuits and Systems, May 2022.
65. Y. J. Tang and X. Zhang, “An efficient parallel architecture for resource-shareable Reed-Solomon encoder,” Proc. of IEEE Workshop on Signal Processing Systems, Oct. 2021.
64. Z. Huai, K. K. Parhi, and X. Zhang, “Efficient architecture for long integer modular multiplication over Solinas prime,” Proc. of IEEE Workshop on Signal Processing Systems, Oct. 2021.
63. J. Zhou and X. Zhang, “A low-complexity flexible logic-locking scheme resisting removal attacks,” Proc. of IEEE International Midwest Symposium on Circuits and Systems, Aug. 2021.
62. Z. Xie and X. Zhang, “Scaled fast nested key equation solver for generalized integrated interleaved BCH decoders,” Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing, Toronto, Canada, Jun. 2021.
61. X. Zhang and K. K. Parhi, “Reduced-complexity modular polynomial multiplication for R-LWE cryptosystems,” Proc. of. IEEE International Conference on Acoustics, Speech, and Signal Processing, Toronto, Canada, Jun. 2021.
60. X. Zhang and Y. J. Tang, “Low-complexity parallel cyclic redundancy check,” Proc. of IEEE International Symposium on Circuits and Systems, Daegu, Korea, May 2021.
59. Y. J. Tang and X. Zhang, “Low-complexity architectures for parallel long BCH encoders,” Proc. of IEEE Workshop on Signal Processing Systems, Coimbra, Portugal, Oct. 2020.
58. X. Zhang, "High-speed and low-complexity parallel long BCH encoder," Proc. of IEEE International Symposium on Circuits and Systems, Seville, Spain, May 2020.
57. J. Zhou and X. Zhang, "A new logic-locking scheme resilient to gate removal attack," Proc. of IEEE International Symposium on Circuits and Systems, Seville, Spain, May 2020.
56. P. Shvartsman and X. Zhang, "Side channel attack resistant AES design based on finite field construction variation," Proc. of IEEE Workshop on Signal Processing Systems, Nanjing, China, Oct. 2019.
55. X. Zhang, "Decoding of generalized three-layer integrated interleaved codes," Proc. of IEEE International Symposium on Information Theory, Paris, France, Jul. 2019.
54. X. Zhang, “Systematic encoder of generalized three-layer integrated interleaved codes,” Proc. of IEEE International Conference on Communications, Shanghai, China, May 2019.
53. X. Zhang, and Y. J. Tang, “Reducing parallel linear feedback shift register complexity through input tap modification,” Proc. of IEEE International Symposium on Circuits and Systems, Sapporo, Japan, May 2019.
52. X. Zhang, P. Shvartsman, J. Zhou, and E. Tawfik, “Hardware obfuscation of AES through finite field construction variation,” Proc. of IEEE International Symposium on Circuits and Systems, Sapporo, Japan, May 2019.
51. A. Sharma, X. Zhang, and Y. Lao, “Hardware obfuscation through reconfigurable finite field arithmetic units,” Proc. of IEEE International Symposium on Circuits and Systems, Sapporo, Japan, May 2019.
50. X. Zhang and M. O’Sullivan, “Ultra-compressed three-error-correcting BCH decoder,” Proc. of IEEE International Symposium on Circuits and Systems, Florence, Italy, May 2018.
49. X. Zhang and A. Bazarsky, “Perfect column-layered two-bit message-passing LDPC decoder and architectures,” Proc. of IEEE International Symposium on Circuits and Systems, Florence, Italy, May 2018.
48. X. Zhang, I. Dror, and S. Alterman, “Low-power partial-parallel Chien search architecture with polynomial degree reduction,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 2459-2462, Montreal, Canada, May 2016.
47. X. Zhang, “Modified trellis-based Min-max decoder for non-binary LDPC codes,” Proc. of International Conference on Computing, Networking and Communications, pp. 613-617, Anaheim, CA, Feb. 2015.
46. X. Zhang and Y. Tai, “High-speed multi-block-row layered decoding for quasi-cyclic LDPC codes,” Proc. of IEEE Global Conference on Signal and Information Processing, pp. 11-14, Atlanta, GA, Dec. 2014.
45. X. Zhang, “Interpolation-based Chase BCH decoder,” Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2014.
44. X. Zhang, F. Cai, and M. P. Anantram, “Low-energy and low-latency error correction for phase change memory,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 1236-1239, Beijing, China, May 2013.
43. F. Cai, X. Zhang, D. Declercq, B. Vasic, D. V. Nguyen, and S. K. Planjery, “Low-complexity finite alphabet iterative decoders for LDPC codes,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 1332-1335, Beijing, China, May 2013.
42. W. Zhang, J. Wang, and X. Zhang, “Low-power design of Reed-Solomon encoders,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 1560-1563, Beijing, China, May 2013.
41. X. Zhang, R. Shi and J. Ritcey, “Reducing the latency of Lee-O’Sullivan interpolation through modified initialization,” Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2013.
40. W. Zhang, X. Zhang and H. Wang, “Increasing the energy efficiency of WSNs using algebraic soft-decision Reed-Solomon decoders,” Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 49-52, Taiwan, Dec. 2012.
39. F. Cai and X. Zhang, “Efficient check node processing architecture for non-binary LDPC decoding using power representation,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 137-142, Quebec City, Canada, Oct. 2012.
38. X. Zhang, F. Cai and R. Shi, “Low-power LDPC decoding based on iteration prediction,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 3041-3044, Seoul, Korea, May 2012.
37. X. Zhang, Y. Zheng, and Y. Wu, “A Chase-type Koetter-Vardy algorithm for soft-decision Reed-Solomon decoding,” Proc. of International Conference on Computing, Networking and Communications, pp. 466-470, Maui, HI, Feb. 2012.
36. X. Zhang, R. Shi and J. Ritcey, “On the implementation of modified fuzzy vault for biometric encryption,” Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2012.
35. X. Zhang and F. Cai, “An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding,” Proc. of Asilomar Conference on Signals, Systems, and Computers, pp. 885-888, Pacific Grove, CA, Nov. 2011.
34. X. Zhang, J. Zhu and Y. Wu, “Efficient one-pass Chase soft-decision BCH decoder for multi-level cell NAND flash memory,” Proc. of IEEE International Midwest Symposium on Circuits and Systems, Seoul, Korea, Aug. 2011.
33. X. Zhang, and F. Cai, “Reduced-memory forward-backward check node processing architecture for non-binary LDPC decoding,” Proc. of IEEE International Midwest Symposium on Circuits and Systems, Seoul, Korea, Aug. 2011.
32. X. Zhang, Y. Wu and J. Zhu, “A novel polynomial selection scheme for low-complexity Chase algebraic soft-decision Reed-Solomon decoding,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 2689-2692, Rio De Janeiro, Brazil, May 2011.
31. X. Zhang and F. Cai, “Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 1303-1306, Rio De Janeiro, Brazil, May 2011.
30. X. Zhang and Y. Zheng, “Efficient codeword recovery architecture for low-complexity Chase Reed-Solomon decoding,” Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2011.
29. X. Zhang and F. Cai, “Reduced-latency scheduling scheme for the Min-max non-binary LDPC decoding,” Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 414-417, Kuala Lumpur, Malaysia, Dec. 2010.
28. X. Zhang and J. Zhu, “Reduced-complexity multi-interpolator algebraic soft-decision Reed-Solomon decoder,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 398-403, San Francisco, CA, Oct. 2010.
27. X. Zhang and F. Cai, “Reduced-complexity check node processing for non-binary LDPC decoding,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 70-75, San Francisco, CA, Oct. 2010.
26. X. Zhang and F. Cai, “Reduced-complexity extended Min-sum check node processing for non-binary LDPC decoding,” Proc. of IEEE International Midwest Symposium on Circuits and Systems, pp. 737-740, Seattle, WA, Aug. 2010.
25. J. Zhu and X. Zhang, “High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 465-468, Paris, France, May 2010.
24. X. Zhang and F. Cai, “Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes,” Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1506-1509, Dallas, TX, Mar. 2010.
22.J. Zhu and X. Zhang, “Efficient generalized minimum-distance decoder of Reed-Solomon codes,” Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1502-1505, Dallas, TX, Mar. 2010.
23. Y. Chen and X. Zhang, “High-speed architecture for image reconstruction based on compressive sensing,” Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1574-1577, Dallas, TX, Mar. 2010.
22. X. Zhang and J. Zhu, “Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons,” Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2010.
21. X. Zhang and J. Zhu, “Interpolation-based hard-decision Reed-Solomon decoders,” Proc. of International Symposium on Integrated Circuits, pp. 175-178, Singapore, Dec. 2009.
20. J. Zhu and X. Zhang, “Factorization-free low-complexity Chase soft-decision decoding of Reed-Solomon codes,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 2677-2680,Taiwan, May 2009.
19. X. Zhang, “High-speed VLSI architecture for low-complexity Chase soft-decision Reed-Solomon decoding”, Proc. of Information Theory and Applications Workshop, San Diego, CA, Feb. 2009.
18. X. Zhang, “VLSI architecture design for algebraic soft-decision Reed-Solomon decoding,” Proc. of Asilomar Conference on Signals, Systems, and Computers, pp. 1518-1522, Pacific Grove, CA, Nov. 2008.
17. J. Zhu and X. Zhang, “Scalable interpolation architecture for soft-decision Reed-Solomon decoding,” Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 41-44, Macao, China, Nov. 2008.
16. Z. Cui, Z. Wang, X. Zhang and Q. Jia, “Efficient decoder design for high-throughput LDPC decoding,” Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 1640-1643, Macao, China, Nov. 2008.
15. Q. Li, Z. Wang, X. Zhang and X. Liu, “Efficient architecture for the Tate pairing in characteristic three,” Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 1111-1115, Macao, China, Nov. 2008.
14. J. Zhu, X. Zhang and Z. Wang, “Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes,” Proc. of IEEE International Conference on Computer Design, pp. 526-531, Lake Tahoe, CA, Oct. 2008.
13. X. Zhang and J. Zhu, “Efficient interpolation architecture for soft-decision Reed-Solomon decoding by applying slow-down,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 19-24, Washington D. C., Oct. 2008.
12. B. Chen and X. Zhang, “Error correction for multilevel NAND flash memory using Reed-Solomon codes,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 94-99, Washington D. C., Oct. 2008.
11. Z. Cui, Z. Wang, X. Zhang and Q. Jia, “Hardware efficient LDPC decoding for magnetic recording,” Proc. of IEEE International Magnetics Conference, Madrid, Spain, May 2008.
10. J. Zhu, X. Zhang and Z. Wang, “Novel interpolation architecture for low-complexity Chase soft-decision decoding of Reed-Solomon codes,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 3078-3081, Seattle, WA, May 2008.
9. B. Chen and X. Zhang, “FPGA implementation of a factorization processor for soft-decision Reed-Solomon decoding,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 944-947, Seattle, WA, May 2008.
8. J. Zhu and X. Zhang, “Efficient interpolation architecture for soft-decision Reed-Solomon decoding,” IEEE Workshop on Signal Processing Systems, pp. 663-668, Oct. 2007.
7. X. Zhang and J. Zhu, “Efficient VLSI architecture for soft-decision Reed-Solomon decoding,” Proc. of 13th NASA Symposium on VLSI, Post Falls, ID, Jun. 2007.
6. X. Zhang and J. Zhu, “Low-complexity interpolation architecture for soft-decision Reed-Solomon decoding,” Proc. of IEEE International Symposium on Circuits and Systems, pp. 1413-1416, New Orleans, LA, May 2007.
5. X. Zhang, “High-speed factorization architecture for soft-decision Reed-Solomon decoding,” Proc. of IEEE International Conference on Computer Design, pp. 370-375, San Jose, CA, Oct. 2006.
4. X. Zhang, “Partial parallel factorization in soft-decision Reed-Solomon decoding,” Proc. of ACM Great Lakes Symposium on VLSI, pp. 272-277, Philadelphia, PA, Apr. 2006. (First Place Student Paper Contest)
3. X. Zhang and K. K. Parhi, “An efficient 21.56 Gbps AES implementation on FPGA,” Proc. of Asilomar Conference on Signals, Systems, and Computers, pp. 465-470, Pacific Grove, CA, Nov. 2004.
2. X. Zhang and K. K. Parhi, “Fast factorization architecture in soft-decision Reed-Solomon decoding,” Proc. of IEEE Workshop on Signal Processing Systems, pp. 101-106, Austin, TX, Oct. 2004.
1. X. Zhang and K. K. Parhi, “High-speed architectures for parallel long BCH encoders,” Proc. of ACM Great Lakes Symposium on VLSI, pp. 1-6, Boston, MA, Apr. 2004. (Best Paper Award)
Teaching
ECE 5560 Advanced Hardware Architecture Design Techniques, Spring 2020-2023
ECE 2060 Introduction to Digital Logic, Fall 2017, 2019, Spring 2021-2023
ECE 5194.08 VLSI Digital Signal Processing Systems, Spring 2018, 2019
ECE 3050 Signals and Systems, Fall 2018, 2019
RA Openings
Prof. Zhang is looking for highly-motivated Ph.D. students to join her lab.
Research assistant positions are available in Fall 2024. Our research translates theoretical advancements to highly efficient practical hardware implementations through integrated algorithmic and architectural optimizations. The focuses of our current research include coding schemes and hardware architecture design for next-generation memories and digital communications, hardware security, homomorphic encryption, post-quantum cryptography, and machine learning. As it has been proved from Dr. Zhang’s academic and industry experience, such research leads to novel techniques and designs that have great impacts on practical systems. Students in this research area are highly valued by both academic institutes and high-tech companies.
Good math background is required. Prior experience on error-correcting coding, cryptography, digital logic design, security, or related topics is preferred.
Interested students may send CV and transcript in pdf to zhang.8952 at osu.edu. General application can be submitted through
https://gpadmissions.osu.edu/apply/grad.html
and the deadline can be extended.
Sometimes, I may not be able to reply to your inquires, but I will keep them on file until your full application is received.
News
Sep. 2023, new paper "Low-complexity parallel Min-sum medium-density parity-check decoder for McEliece cryptosystem” accepted by IEEE Transactions on Circuits and Systems-I. This is the first paper addressing scaled Min-sum decoder design for MDPC codes.
Sep. 2023, Prof. Zhang will be the Associate Editor-in-Chief of TCAS-I, 2023-2024.
Jul. 2023, new paper "Fast and low-complexity soft-decision generalized integrated interleaved decoder” accepted by IEEE Journal on Selected Areas in Information Theory.
Jun. 2023, new paper "Joint protection scheme for deep neural network hardware accelerators and models" accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Apr. 2023, Congratulations to Jingbo Zhou for successfully defending his thesis!
Nov. 2022, Prof. Zhang presented her work on hardware security and accelerator design at Micron.
Aug. 2022, Prof. Zhang will give a talk "Generalized integrated interleaved codes for hyper-speed memories” in Flash Memory Summit 2022.
Jul. 2022, new paper “Algorithmic obfuscation for LDPC decoders” accepted by IEEE Transactions on Computer-Aided Design. To the best of our knowledge, this is the first paper addressing logic locking for circuits implementing self-correcting or fault-tolerating algorithms.
Jun. 2022 new paper “Low-latency nested decoding for short generalized integrated interleaved BCH codes" accepted by IEEE Trans. on VLSI Systems. Our GII decoder now can achieve Terabyte/s decoding throughput with low complexity and short latency.
Apr. 2022, Congratulations to Zhenshan Xie for successfully defending his thesis! Now he is officially Dr. Xie.
Apr. 2022, Prof. Zhang received the College of Engineering Lumley Research Award
Jan. 2022, new paper “Improved miscorrection detection for generalized integrated interleaved BCH codes” accepted by ICC 2022.
Jan. 2022, three papers accepted by ISCAS 2022
Efficient check node processing for Min-Max NB-LDPC decoding over lower-order finite fields. Low-complexity AES architectures resilient to power analysis attacks. Efficient nested key equation solver for short generalized integrated interleaved BCH codes.
Dec. 2021, Prof. Zhang was elected the Vice President-Technical Activities of the IEEE Circuits and Systems Society.
Oct. 2021, new paper “A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA and GPU architectures” has been accepted by IEEE Communications Surveys and Tutorials.
Oct. 2021, new paper "Low-complexity resource-shareable parallel generalized integrated interleaved encoder” has been accepted by TCAS-I. For the first time, an efficient parallel GII encoder is developed.
Jul. 2021, two papers accepted by SiPS 2021
An efficient parallel architecture for resource-shareable Reed-Solomon encoder Efficient architecture for long integer modular multiplication over Solinas prime
Jun. 2021, Our paper "Efficient sub-codeword key equation solver for generalized integrated interleaved BCH decoder" has been accepted by TCAS-II. Our architecture can achieve three times higher efficiency than prior designs.
Jun. 2021, Prof. Zhang is elected as the Chair of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society. High-speed and reliable data access is the key enabler of many new technologies, such as cloud computing, hyper-speed data analytics, and machine learning. Please consider joining our TC if you are interested in data storage.
Apr. 2021, Our new paper "Miscorrection mitigation for generalized integrated interleaved BCH codes" gets accepted by IEEE Communications Letters. Low-complexity miscorrection detection and mitigation schemes have been developed to improve the actual performance of short GII-BCH codes by orders of magnitude.
Mar. 2021, Prof. Zhang will give an overview lecture at ISCAS 2021 on "Generalized and Algorithmic Logic Locking".
Feb. 2021, Our new paper "Fast en/decoding of Reed-Solomon codes for failure recovery" has been accepted by IEEE Transactions on Computers. Variations on finite field construction also leads to faster Reed-Solomon en/decoders in software implementation.
Feb. 2021, Our new paper "Generalized SAT-attack-resistant logic locking" has been accepted by IEEE Transactions on Information Forensics and Security. Our design can construct SAT-attack-resilient logic-locking blocks using a large variation of complementary or non-complementary functions. Many existing designs are special cases of our design.
Jan. 2021, three papers accepted by ISCAS 2021 and ICASSP 2021.
Scaled fast nested key equation solver for generalized integrated interleaved BCH decoders Reduced-complexity modular polynomial multiplication for R-LWE cryptosystems Low-complexity parallel cyclic redundancy check
Sep. 2020, our new paper "Fast nested key equation solvers for generalized integrated interleaved decoder," has been accepted by TCAS-1. This work made another big improvement on the GII decoder design. The latency of the KES step is reduced by 50% with very small area overhead.
Aug. 2020, a new review paper "VLSI architectures for Reed-Solomon codes: classic, nested, coupled, and beyond” has been accepted by the IEEE Open Journal of Circuits and Systems. This paper provides comprehensive understanding of state-of-the-art VLSI architectures for classic RS/BCH codes and introduces the most recent architectures for new coding schemes built by nesting/coupling RS/BCH codes for emerging applications.
Jul. 2020, new paper "Low-complexity architectures for parallel long BCH encoders" accepted by IEEE Workshop on Signal Processing Systems 2020.
Jun. 2020, new paper "Reduced-complexity key equation solvers for generalized integrated interleaved BCH decoders" accepted by TCAS-I.
Feb. 2020, Prof. Zhang will give a talk at ITA workshop on efficient hardware architecture design for the nested key equation solver in generalized integrated interleaved decoders.
Feb. 2020, new paper "Scaled nested key equation solver for generalized integrated interleaved decoder" accepted by TCAS-II.
Jan. 2020, Prof. Zhang will give an overview talk at ISCAS 2020 on "VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond".
Jan. 2020, two papers accepted by ISCAS 2020.
High-Speed and Low-Complexity Parallel Long BCH Encoder A New Logic-Locking Scheme Resilient to Gate Removal Attack
Nov. 2019, new paper "Efficient VLSI architectures for coupled-layered regenerating codes" accepted by TCAS-II.
Aug. 2019, new paper "Side channel attack resistant AES design based on finite field construction variation" accepted by IEEE Workshop on Signal Processing Systems 2019.
Jul. 2019, new paper "Relaxing the constraints on locally recoverable erasure codes by finite field element variation," accepted by IEEE Communications Letters.
Jul. 2019, Prof. Zhang will give a talk "Improving the locality of generalized integrated interleaved codes" at the Flash Memory Summit 2019.
May 2019, our new paper "Efficient architectures for generalized integrated interleaved decoder" has been accepted by TCAS-I. With excellent error-correcting performance, our decoder can easily achieve more than 40GByte/s throughput.
Apr. 2019, Prof. Zhang is going to give a talk at UC Irvine on "Error-Correcting Codes for Hyper-Speed Distributed Storage: from Theory to Practice"
Apr. 2019, our paper "Decoding of generalized three-layer integrated interleaved codes," has been accepted by ISIT 2019.
Mar. 2019, our new paper "On the construction of composite finite fields for hardware obfuscation," has been accepted by the IEEE Transactions on Computers.
Feb. 2019, Prof. Zhang is serving as the Technical Program Chair of the IEEE Workshop on Signal Processing Systems SiPS 2019. Please consider submitting a paper.
Feb. 2019, the following paper is accepted by ICC 2019
Systematic Encoder of Generalized Three-Layer Integrated Interleaved Codes
Jan. 2019, We have two papers accepted by ISCAS 2019
Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification Hardware Obfuscation of AES Through Finite Field Construction Variation
Jan. 2019, Prof. Zhang was elected to serve on the Board of Governors of the IEEE Circuit and Systems Society for the term 2019-2021
Jan. 2019, Prof. Zhang will give a talk at the ITA 2019 workshop on the en/decoding of three-layer generalized integrated interleaved codes
Dec. 2018, Prof. Zhang has been elected to be the Vice-Chair from Academia of the Data Storage Technical Committee of the IEEE Communications Society for the 2019-2020 term.
Oct. 2018, Prof. Zhang gave a talk at Cybersecurity Days at OSU about hardware obfuscation through algorithmic modifications.
Sep. 2018, Prof. Zhang is serving as the Chair of the Data Storage Track of ICC 2019. Please consider submitting a paper.
Mar. 2018, Prof. Zhang will give a talk at the University of Minnesota on error-correcting codes.
Feb. 2018, Prof. Zhang will give a tutorial on "Error-Correcting Decoder Design for Next-Generation Memories: From Theory to Practice" at ISCAS 2018.
Feb. 2018, Our two papers on "Ultra-compressed three-error-correcting BCH codes, and "Perfect column-layered two-bit message-passing LDPC decoder" will be presented at ISCAS 2018.
Jan. 2018, Prof. Zhang will give a talk at the ITA workshop on improving the locality of generalized integrated interleaved codes.
Dec. 2017, My paper "Generalized Three-Layer Integrated Interleaved Codes" was accepted by IEEE Communications Letters.
Dec. 2017, Prof. Zhang was re-appointed as an associate editor for TCAS-1. She has been serving on this editorial board since 2010.
Dec. 2017, Prof. Zhang gave a talk on extending the theory of error-correcting codes to improve the performance of next-generation applications at Fudan University and Nanjing University.
Nov. 2017, Prof. Zhang is serving as the Tutorial Co-Chair of SiPS 2018. Please consider submitting a tutorial proposal.
Oct. 2017, Prof. Zhang co-organized a special session on "Error-Correcting Codes for Next-Generation Memories" for ISCAS 2018.
Students
Current students:
Sajjad Akherati, Ph.D (08/2022-)
Research topics: Homomorphic encryption
Jiaxuan Cai, Ph.D (08/2022-)
Research topics: Post-quantum cryptography
Yok Jye Tang, Ph.D (01/2020-)
Research topics: Advanced error-correcting codes
Alumni:
Jingbo Zhou, Ph.D. (09/2018-05/2023)
Thesis: Hardware Security: Protecting the Intellectual Property of Integrated Circuits
First employment: Postdoc at University of Florida
Zhenshan Xie, Ph.D (09/2018-05/2022)
Thesis: Efficient Hardware Implementation Architectures for Generalized Integrated Interleaved Decoder
First employment: Synopsys
Phillip Shvartsman, MS (01/2018-04/2019)
Thesis: Side-Channel-Attack Resistant AES Design Based on Finite Field Construction Variation
First employment: Northrop Grumman