PMRL Research Topics

Mixed-signal SoCs include a large number of system sub-components that are integrated together in a single nanometer CMOS chip, with each sub-components typically requiring its own independent and well-isolated power supply. Moreover, with the diminishing returns of technology scaling in terms of reducing power consumption, the industry is moving away from using static power supply levels and adopting instead a dynamic approach. In such approach, the power supplies are dynamically adapted based on the real-time demand of the sub-components in order to better manage and reduce the overall power consumption of the system. This approach can be applied, in theory, at any granularity where each sub-component is further divided into yet smaller sub-components with their own separate power supplies. Thus, as SoCs grow, the number of independent power supplies becomes large, and implementing them in a size- and cost-effective manner becomes challenging. This is due to the fact that power supplies require passive components that often can’t be integrated on chip, and thus the Bill of Material (BOM), package pin count of the SoC, and Printed Circuit Board (PCB) area become large and costly. Moreover, as dynamic powering becomes more dominant, these power supplies need to have fast dynamic performance, which traditionally comes at the expense of much degraded power conversion efficiency.

The focus of this research is to address the above challenges by developing new power supply architectures that enable the implementation of a large number of highly dynamic and efficient on-chip power supplies, i.e. on-chip power supply grids.

Related Publications:

1. Y. Jiang, S. Asar, M. Ahmed, H. Zhang, and A. Fayed, “Output Control Techniques for Dual-Frequency SIMO Buck Converters,” IEEE Transactions on Circuits & Systems I, vol. 66, no. 10, pp. 4055-4067, Oct. 2019.

2. S. Asar, H. Zhang, and A. Fayed, “Dual-Frequency SIMO Topologies for On-Chip Dynamic Power Supplies,” 2018 IEEE Power Supply on Chip Workshop (PWRSoC), Hsinchu, Taiwan, Oct. 2018. Poster.

3. Yongjie Jiang and Ayman Fayed, “A 1A, Dual-Inductor 4-Output Buck Converter with 20-MHz/100-MHz Dual-Frequency Switching and Integrated Output Filters in 65nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2485-2500, Oct. 2016.

4. Chih-Wei Chen and Ayman Fayed, “A Low-Power Dual-Frequency SIMO Buck Converter Topology with Fully-Integrated Outputs and Fast Dynamic Operation in 45-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2161-2173, Sept. 2015.

5. Chih-Wei Chen, Jeffrey Morroni, David Anderson, and Ayman Fayed, “Dual-Frequency SIMO Power Converters for Low-Power on-Chip Power Grids in SoCs,” 2014 IEEE Applied Power Electronics Conference (APEC), Fort Worth, Texas, Mar. 2014, pp. 1954-1957.

6. Yongjie Jiang and Ayman Fayed, “A 1A, 20MHz/100MHz Dual-Inductor 4-Output Buck Converter with Fully-Integrated Bond-Wire-Based Output Filters for Ripple Reduction,” 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, Sept. 2015, pp. 1-4.

7. Wei Fu and Ayman Fayed, “Power Conversion Schemes in Mixed-Signal SoCs,” 2014 IEEE Int. symposium on circuits and Systems (ISCAS), Melbourne VIC, Australia, Jun. 2014, pp. 606-609.

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The off-chip passive components (inductors and capacitors) in conventional switching power converters are becoming increasingly difficult to accommodate in many electronic devices due to their high cost and large footprint. This difficulty is exacerbated by the fact that many that many of these devices now require a large number of separate power supplies in order to manage power consumption and avoid coupling effects between the different parts of the system.

This research focuses on leveraging the dramatic scaling in CMOS technologies to build switching power converters with very high switching frequencies in order to reduce the size of passive components to levels where they can be implemented on chip or on package substrates while achieving higher power conversion efficiency than on-chip linear alternatives.

Related Publications:

1. M. Singh and A. Fayed, “A 1-A 6-MHz Digitally-Assisted Buck-Boost Converter with Seamless Mode Transitions and Fast Dynamic Performance for Mobile Devices,” IEEE Tran. on Power Electronics, vol. 36, no. 4, pp. 4338-4351, Apr. 2021. Received the 2021 IEEE Tran. on Power Electronics Second Place Prize Paper Award.

2. M. Singh and A. Fayed, “A 2-A 6-MHz Hysteretic Buck Converter with an 8-Bit Digital Jitter-Insensitive Frequency Correction Loop using Dual-Sided Hysteretic Band Modulation,” 2020 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, Aug. 2020, pp. 754-757.

3. M. Abdelfattah, M. Swilam, B. Dupaix, S. Smith, A. Fayed, and W. Khalil, “An On-Chip Resonant-Gate-Drive Switched-Capacitor Converter for NearThreshold Computing Achieving 70.2% Efficiency at 0.92A/mm2 Current Density and 0.4V Output,” 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018, pp. 438-440.

4. M. Singh and A. Fayed, “An 8 A 100-MHz 4-Phase Buck Converter with Fast Dynamic Response and Enhanced Light-Load Efficiency,” 2018 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, Canada, Aug. 2018, pp. 861-864.

5. Wei Fu, and Ayman Fayed, “A Feasibility Study of High-Frequency Buck Regulators in Nanometer CMOS Technologies,” 2009 IEEE Dallas circuits & Systems Workshop (DCAS), Dallas, Texas, Oct. 2009, pp. 31-34.

6. Wei Fu and Ayman Fayed, “A Self-Regulated 588 MHz Buck Regulator with On-chip Passives and Circuit Stuffing in 65nm,” 2014 IEEE Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, Aug. 2014, pp. 338-341. Recipient of best student paper award (shared with other papers).

7. Wei Fu and Ayman Fayed, “Power Conversion Schemes in Mixed-Signal SoCs,” 2014 IEEE Int. symposium on circuits and Systems (ISCAS), Melbourne VIC, Australia, Jun. 2014, pp. 606-609.

8. Yongjie Jiang and Ayman Fayed, “On-Chip Input and Ground Ringing Suppression in High-Frequency Buck Converters,” 2015 Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, Colorado, Aug. 2015, pp. 1-4.

9. Wei Fu, Siang Tan Tong, and Ayman Fayed, “Switching and Conduction Loss Analysis of Buck Converters Operating in DCM-only Scenarios,” 2013 IEEE Int. symposium on circuits and Systems (ISCAS), Beijing, China, May 2013, pp. 921-924.

10. Yogesh K. Ramadass, Ayman A. Fayed, and Anantha P. Chandrakasan, “A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2557-2565, Dec. 2010.

11. Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, and Anantha P. Chandrakasan, “A 0.16mm2 Completely On-Chip Switched-Capacitor DC-DC Converter using Digital Capacitance Modulation for LDO Replacement in 45nm CMOS,” 2010 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2010, pp. 209-210,209a.

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The high breakdown voltage and temperature resiliency of Silicon Carbide (SiC) makes it an attractive technology for designing power converters in a variety of applications, including high-voltage power management ICs, Point of Load (PoL) Converters, and DC-DC converters for distributed power generation systems ; battery management ICs and automotive on-board charging; and harsh environment and aerospace applications. Existing power converter solutions use SiC only for the realization of the power switches, while the gate drivers and any other low-voltage analog and mixed-signal control and processing circuitry are typically realized in a separate silicon CMOS chip. These multi-chip solutions significantly increase the complexity, cost, and footprint of the design, and in applications where the power converter must tolerate high temperature, such as subterranean exploration and monitoring in oil, gas and geothermal exploration, such approach requires large physical separation between the low-voltage gate-drivers and the control and processing circuits implemented in silicon CMOS on the one side, and the power stage implemented in SiC on the other side. This large physical separation may not be feasible in some applications and further complicates the design and increases cost and footprint. Thus, there is a need for fully integrating high-voltage power switches with low-voltage gate-drivers and other analog and mixed-signal processing circuits together in the same SiC chip.

The focus of this research is to enable realizing multiple independent high-voltage power converters with their low-voltage analog/mixed-signal control and driving circuits on the same chip for complete single-chip fully-integrated power solutions.

Related Publications:

1. H. Zhang, T. Liu, U. Gupta, S. B. Isukapatiy, E. Ashik, A. J. Morgan, B. Lee, W. Sung, A. K. Agarwal, and A. Fayed, “A 600V Half-Bridge Power Stage Fully Integrated with 25V Gate-Drivers in SiC CMOS Technology,” 2022 IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), Fukuoka, Japan, Aug. 2022, pp. 1-4.

2. E. Ashik, S. Isukapati, H. Zhang, T. Liu, U. Gupta, A. Morgan, V. Misra, W. Sung, A. Fayed, A. Agarwal, B. Lee, “Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications,” 2022 IEEE International Reliability Physics Symposium (IRPS), Mar. 2022, pp. 3B.4-1 to 3B.4-8.

3. T. Liu, H. Zhang, S. B. Isukapatiy, E. Ashik, A. J. Morgan, B. Lee, W. Sung, A. Fayed, M. H. White, and A. K. Agarwal, “SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology,” IEEE Journal of the Electron Devices Society, vol. 10, no. 2, pp. 129-138, Feb. 2022.

4. S. B. Isukapati, H. Zhang, T Liu, E. Ashik, B. Lee, A. J. Morgan, W. Sung, A. Fayed, A. K. Agarwal, “Development of Isolated CMOS and HV MOSFET on an N-epi/P-epi/4H-SiC N+ Substrate for Power IC Applications,” 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WIPDA), Nov. 2021, pp. 118-122.

5. T. Liu, H. Zhang, S. B. Isukapatiy, E. Ashik, A. J. Morgan, B. Lee, W. Sung, M. H. White, A. Fayed, and A. K. Agarwal, “SPICE Modeling and CMOS Circuit Development of a SiC Power IC Technology,” 2021 IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), East Lansing, Michigan, Aug. 2021, pp. 966-969.

6. S. B. Isukapati, H. Zhang, T Liu, E. Ashik, B. Lee, A. J. Morgan, W. Sung, A. Fayed, A. K. Agarwal, “Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology,” 2021 IEEE 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, Jun. 2021, pp. 267-270. Recipient of best poster presentation award.

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• Power conversion/modulation in GaN

• Data converters design for wireless and multimedia applications

• High-speed wire-line transceivers design for digital communication systems: Adaptive equalizers, Adaptive signal drivers/receivers, Adaptive filters, and clock and data recovery circuits

• Low-voltage, low-power design in nanometer CMOS technologies

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