First Ohio State student to win prestigious ISSCC award
For the first time, an electrical and computer engineering (ECE) student at The Ohio State University won a prestigious award for his research in solid-state circuits technology.
ECE student Jack Hsueh received the Analog Devices (ADI) Outstanding Student Designer Award at the 2018 International Solid-State Circuits Conference (ISSCC) starting Feb. 11.
The event is the flagship gathering of scientists presenting cutting-edge research in circuit design.
Solid-state electronic devices are part of every day technology, from radios and amplifiers, to LED computer monitors and TV remote controls. Solid-state devices, such as a transistor, use conductors to control the flow of signals through a circuit. In digital circuits, an integrated circuit chip is a collection of transistors and wires that hook them together.
Vanessa Chen, said the award is prestigious and marks the first time Ohio State research was highlighted among the winners.Hsueh’s faculty advisor, ECE Assistant Professor
“Past winners were from schools like MIT, Berkeley and Stanford,” Chen said. “Having Ohio State on the map is phenomenal.”
Chen said the award is given to highlight excellence in integrated circuit design, and is initiated by the director of the High-Speed Data Converter group and the director of the University Program at ADI.
“Through this award, we hope to engage more closely with ADI on research in the area of data converters and start building a strong link,” Chen said.
Hsueh received his B.S. and M.S. degrees in Electrical and Electronic Engineering from National Cheng Kung University and National Taiwan University, Taiwan, in 2010 and 2013, respectively. He received his M.S. degree in ECE from Ohio State in 2017. He is currently working toward a doctoral degree at Ohio State. His research is focused on bio-inspired computing with next-generation massive storage.
From 2011 to 2014, Hsueh was a research assistant, designing beamforming analog front-end circuits. As a Ph.D. student, he develops energy-efficient architectures and algorithms for high-speed ADCs, including a 6-bit 7GS/s ADC for 60-GHz wireless transceivers with a two-stage topology.
Combining the design experience of the multiple-channel beamforming arrays and high-speed ADCs, he is exploring neuro-inspired algorithms to build low-power computationally intelligent ADCs. The novel interface is expected to enable rapid analysis of complex information directly at the RF/mixed-signal front-end. Because only pre-processed information needs to be transmitted or stored for backend computing, massive data access to memory and processors is reduced significantly. Therefore, the low-complexity mixed-signal processing engine can maximize spectrum usage and achieve better energy efficiency.