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Cadence Central

Cadence University Program Member

Department of Electrical & Computer Engineering
The Ohio State University

The Cadence toolset is a complete microchip EDA system, which is intended to develop professional, full-scale, mixed-signal microchips and breadboards.  The modules included in the toolset are for schematic entry, design simulation, data analysis, physical layout, and final verification.  The Cadence tools at The Ohio State University are the same as those at most every professional mixed-signal microelectronics company in the United States.  The strength of the Cadence tools is in its analog design/simulation/layout and mixed-signal verification and is often used in tandem with other tools for RF and/or digital design/simulation/layout, where complete top-level verification is done in the Cadence tools.

Another important concept is that the Cadence tools only provide a framework for doing design. Without a foundry-provided design kit, no design can be done.  Hence, provided below are instructions on how to setup an OSU ECE account for using Cadence tools, then below that are instructions are how to setup various design kits presently on the ECE system. We recommend that every user: setup the base Cadence tools, then setup the NCSU Cadence design kit (CDK) for the MOSIS SCMOS processes under the ICFB (Integrated Circuit Front to Back) tools. [Front end design refers to schematic design and simulation, while back refers to layout and fabrication implementation.]

It is not necessary to install any of the other design kits, although users may want to setup the AMS CSX design kit separately if they would like to go through the ee323 Cadence tutorial examples written by J. Zohios.  Also, we strongly recommend using the directory structures/names presented in the Cadence setup instructions below.  Further, do not run ICFB in your root directory; the files that are created by one design kit can interfere with other ones.

The Cadence Disclaimer:

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence Links

Learning about Cadence Products

Cadence Toolset Setup

  1. To use Cadence, make a cadence directory (~/cadence/)
    • mkdir ~/cadence
  2. Then source the ER4 system Cadence ICFB configuration file.
    • source /opt/local/cadence/Startup.EE
  3. To run generic Cadence ICFB (Virtuoso Toolset) at the command line, use the following commands in the cadence directory (Note: Without a process design kit, no simulation or layout can be done, so running ICFB is pointless until a design kit has been setup):
    • source /opt/local/cadence/Startup.EE
    • icfb &
  • Cadence Design Kit for the MOSIS SCMOS processes (Cadence ICFB) developed by NCSU primarily with additional resources from OSU, VT, UT, and IIT
    1. Make a subdirectory for work using the NCSU CDK (~/cadence/NCSU/)
      • mkdir ~/cadence/NCSU
    2. Then copy all of the NCSU CDK user files and the ER4 ICFB and MGC Artist Link configuration file into this NCSU work directory. [Note: you will want to make symbolic links for the '.cdsinit' file, the 'config_ncsu_current' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'cds.lib' file will be modified, so you will need your own copy.]
      • ln -s /opt/local/cadence/Startup.EE ~/cadence/NCSU/config_icfb
      • ln -s /opt/local/cadence/design_kits/ANACAD/artist_link/current/cdsLibMgr.il ~/cadence/NCSU/.
      • cp /opt/local/cadence/design_kits/NCSU/current/local/user_files/cds.lib ~/cadence/NCSU/.
      • ln -s /opt/local/cadence/design_kits/NCSU/current/local/user_files/.cdsinit ~/cadence/NCSU/.
      • ln -s /opt/local/cadence/design_kits/NCSU/current/local/user_files/config_ncsu_current ~/cadence/NCSU/config_ncsu
    3. To run ICFB at the command line in the NCSU work directory (~/cadence/NCSU/), use the following command:
      • source config_icfb
      • source config_ncsu
      • icfb &
    4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
      • Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
      • Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_ami06).
      • Each design library must be attached to a technology file.
      • The foundy-process-size_TechLib library is the technology file to which the design library should be attached for the given foundry process.
    5. EDA design kits are much like device models, in that they are never perfectly accurate and always continually growing. If you are doing research involving microchip design, you will want your CDK to be as up-to-date & advanced as possible and should use the following commands for the 'beta' version of the NCSU CDK. This version is not an 'alpha' version and has been tested for stability. Plus, the most advanced, time-saving tools that we can find are provided in this CDK. If time and accuracy are important to your research, use the 'beta' version.
      • rm ~/cadence/NCSU/.cdsinit
      • rm ~/cadence/NCSU/config_ncsu
      • ln -s /opt/local/cadence/design_kits/NCSU/beta/local/user_files/.cdsinit ~/cadence/NCSU/.
      • ln -s /opt/local/cadence/design_kits/NCSU/beta/local/user_files/config_ncsu_beta ~/cadence/NCSU/config_ncsu
  • AMS Design Kit for the 0.35um CSX process (Cadence ICFB)
    1. Make a subdirectory for work using the AMS CDK (~/cadence/AMS_CSX/)
      • mkdir ~/cadence/AMS_CSX
    2. Then copy all of the AMS CDK user files and the ER4 ICFB configuration file into this AMS CSX work directory. [Note: you may wish to make symbolic links for the 'config_ams' file and the 'config_icfb' file, so that your configurations will always be up-to-date.]
      • ln -s /opt/local/cadence/Startup.EE ~/cadence/AMS_CSX/config_icfb
      • ln -s /opt/local/cadence/design_kits/AMS/current/user_files/config_ams ~/cadence/AMS_CSX/.
    3. To run ICFB at the command line in the AMS CSX work directory (~/cadence/AMS_CSX/), use the following commands:
      • source config_icfb
      • source config_ams
      • ams_cds -tech csx -tool artist -mode fb &
    4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
      • Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
      • Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_amscsx).
      • Each design library must be attached to a technology file.
      • TECH_CSD is the technology file directory to which each design library should be attached for the AMS CSX process.
  • Design Kit for MITLL AST 0.18um FDSOI CMOS process (Cadence ICFB)
    1. Make a subdirectory for work using the AMS CDK (~/cadence/mitllfdsoi0p18um/)
      • mkdir ~/cadence/mitllfdsoi0p18um
    2. Then copy all of the mitllfdsoi0p18um CDK user files and the ER4 ICFB configuration file into this mitllfdsoi0p18um work directory. [Note: you may wish to make symbolic links for the '.cdsinit' file, the 'config_mitllfdsoi0p18um' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'local.il' file is for your customizations you may want, and the 'cds.lib' file will be modified, so you will need your own copies.]
      • ln -s /opt/local/cadence/Startup.EE ~/cadence/mitllfdsoi0p18um/config_icfb
      • cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/cds.lib ~/cadence/mitllfdsoi0p18um/.
      • ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/.cdsinit ~/cadence/mitllfdsoi0p18um/.
      • cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/local.il ~/cadence/mitllfdsoi0p18um/.
      • ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/config_mitllfdsoi0p18 ~/cadence/mitllfdsoi0p18um/.
    3. To run ICFB at the command line in the mitllfdsoi0p18um work directory (~/cadence/mitllfdsoi0p18um/), use the following  commands:
      • source config_icfb
      • source config_mitllfdsoi0p18
      • icfb &
    4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
      • Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
      • Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_mitllfdsoi0p18um).
      • Each design library must be attached to a technology file.
      • TECHLIB is the technology file directory to which each design library should be attached for the mitllfdsoi0p18um process.
  • Design Kit for MITLL AST FDSOI 0.25um CMOS process (Cadence ICFB)
    1. Make a subdirectory for work using the AMS CDK (~/cadence/mitllfdsoi0p25um/)
      • mkdir ~/cadence/mitllfdsoi0p25um
    2. Then copy all of the mitllfdsoi0p25um CDK user files and the ER4 ICFB configuration file into this mitllfdsoi0p25um work directory. [Note: you may wish to make symbolic links for the '.cdsinit' file, the 'config_mitllfdsoi0p25um' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'local.il' file is for your customizations you may want, and the 'cds.lib' file will be modified, so you will need your own copies.]
      • ln -s /opt/local/cadence/Startup.EE ~/cadence/mitllfdsoi0p25um/config_icfb
      • cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/cds.lib ~/cadence/mitllfdsoi0p25um/.
      • ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/.cdsinit ~/cadence/mitllfdsoi0p25um/.
      • cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/local.il ~/cadence/mitllfdsoi0p25um/.
      • ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/config_mitllfdsoi0p25 ~/cadence/mitllfdsoi0p25um/.
    3. To run ICFB at the command line in the mitllfdsoi0p25um work directory (~/cadence/mitllfdsoi0p25um/), use the following  commands:
      • source config_icfb
      • source config_mitllfdsoi0p25
      • icfb &
    4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
      • Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
      • Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_mitllfdsoi0p25um).
      • Each design library must be attached to a technology file.
      • LVASOI1_TechLib is the technology file directory to which each design library should be attached for the mitllfdsoi0p25um process.
    • Cadence Design Kit for the MOSIS TSMC processes (Cadence ICFB)
      1. Make a subdirectory for work (~/cadence_TSMC/)
        • mkdir ~/cadence_TSMC
      2. Then copy all of the Design Kit user files. For TSMC 0.13.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/.cdsinit ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/cds.lib ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/display.drf ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/pinTextMapTable ~/cadence_TSMC/.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/models ~/cadence_TSMC.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/Calibre ~/cadence_TSMC.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc013v13b/ForUsers/Assura ~/cadence_TSMC.
      3. For TSMC 0.18.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/.cdsinit ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/cds.lib ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/display.drf ~/cadence_TSMC/.
        • cp /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/pinTextMapTable ~/cadence_TSMC/.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/models ~/cadence_TSMC.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/Calibre ~/cadence_TSMC.
        • ln -s /opt/local/cadence/design_kits/TSMC/tsmc018v13d/ForUsers/Assura ~/cadence_TSMC.
      4. To run ICFB at the command line in the cadence_TSMC work directory(~/cadence_TSMC/), use the following command:
        • source /apps/cadence/Startup514.EE
        • icfb &
        • source /apps/cadence/Startup514.EE
        • icfb &

 

Cadence Design Kit for the MOSIS IBM processes (Cadence ICFB)

  1. Make a subdirectory for work (~/cadence_IBM/)
    • mkdir ~/cadence_IBM
  2. Then copy all of the Design Kit user files.
  3. For IBM 90nm and cadence 5.14.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_514/.cdsinit ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_514/.cdsenv ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_514/.simrc ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_514/cds.lib ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_514/display.drf ~/cadence_IBM/.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Spectre/models ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Calibre ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Assura ~/cadence_IBM.
  4. For IBM 90nm and cadence 6.11.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_611/.cdsinit ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_611/.cdsenv ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_611/.simrc ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_611/cds.lib ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_90n/cadence_611/display.drf ~/cadence_IBM/.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Spectre/models ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Calibre ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cms9flp/V1.4.0.0IBM/Assura ~/cadence_IBM.
  5. For IBM 65nm and cadence 5.14.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_514/.cdsinit ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_514/.cdsenv ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_514/.simrc ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_514/cds.lib ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_514/display.drf ~/cadence_IBM/.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Spectre/models ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Calibre ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Assura ~/cadence_IBM.
  6. For IBM 65nm and cadence 6.11.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_611/.cdsinit ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_611/.cdsenv ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_611/.simrc ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_611/cds.lib ~/cadence_IBM/.
    • cp /opt/local/cadence/design_kits/IBM/IBM_CMOS/ForUsers_65n/cadence_611/display.drf ~/cadence_IBM/.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Spectre/models ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Calibre ~/cadence_IBM.
    • ln -s /opt/local/cadence/design_kits/IBM/IBM_CMOS/IBM_PDK/cmos101pe/V1.2.0.0RF/Assura ~/cadence_IBM.
  7. To run ICFB at the command line in the cadence_IBM work directory (~/cadence_IBM/), use the following command for cadence 5.14:
    • source /apps/cadence/Startup514.EE
    • icfb &
  8. To run ICFB at the command line in the cadence_IBM work directory (~/cadence_IBM/), use the following command for cadence 6.11:
    • source /apps/cadence/Startup611.EE
    • virtuoso &

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.
Updated by Amneh Akour, Dec. 18, 2009   


Just some tips about LVSing in Cadence...

Using the NCSU design kit... On the layout window's toolbar -> NCSU -> Modify LVS Rules, set all of the options to be checked (except "Ignore Body Terminal").

In the LVS window, by default set only Rewiring and Terminals option. Device Fixing and Cross Reference can lead to misleading results if you do not know what you are doing.

When reading the output file, concentrate first on unmatched nets and terminals. The netbad.out, mergenet.out, and termbad.out will be the most helpful sections in diagnosing which nets and terminals are miswired. Start with these first.

Ignore the audit.out until you get the netlists to match logically. Then you can go fix device sizes. Also, if LVS misinterprets which device is which, these errors will be dubious anyway.

If you get a huge number of errors by climbing on simple heirarchical step, you probably have a ground or supply miswiring.

If you get mergenet.out report in the layout only, you can search for the layout nets OR uncheck Rewiring in the LVS panel and rerun LVS. This will disallow net merging by LVS and tell you in the netbad.out of the schematic section which schematic net is not connected.

A hint about the message merged nets... it does not mean you have a short, but that LVS had to merge the nets together in order to maximally match schematic and layout. The missing connection is in the view in which the error appears, or may indicate an accidental short in the other view.

If you have run LVS and make no changes to the layout/extracted view and re-run LVS, uncheck the extracted button in the LVS window; the LVS run will go much faster. Likewise with the schematic button.

The rules file is almost always called divaLVS.rul and is located in the technology library for your design (until you modify the LVS rules, then the divaLVS.rul file will be copied to your project library).

by John Sheridan Fisher  


Top Level Integration Methods

Project Hierarchy:

  • top_level (not necessary for class projects)
    • finishing_cells (contains scribe lane, rev block, etc; not nec.)
    • asic_core_pads (required for class projects)
      • padframe (required for class projects)
      • asic_core (required for class projects)

Methodology:

  • Copy the padframe cell but NO pads to your own project directory, then swap in the pads that you need into the layout and schematic. Be very CAREFUL not to move any structures in the padframe layout; any unintentional movement will cause the pads (and thus your design) to fail.
  • Your project core should be called asic_core, which should include routing to the pad pins.
  • The layout to be submitted to the foundry should be called asic_core_pads, which may ONLY, ONLY have asic_core & padframe in it, NO routing or other structures.
  • The layout asic_core must be DRC'ed & LVS'ed, while the layouts padframe & asic_core_pads must (only) be LVS'ed.
  • Once a vddpad and gndpad have been swapped into your padframe layout, please delete the VDD and GND pins from the padframe schematic.
  • Once the padframe schematic with the proper pads has passed LVS, I recommend copying the padframe schematic as the asic_core_pads schematic; making a symbol for the asic_core schematic, which passed DRC & LVS and whose pins are in the same order and orientation as the pad frame pins; and of course inserting and wiring the asic_core symbol into the asic_core_pads schematic.

written by john s. fisher

 


Hints & Tips

  1. Unlocking cells:
    Everytime a design is open for editing, Cadence locks it so that no other process (or somebody else) can change it. It's a security feature.
    Whenever Cadence crashes, it may happen that a design is left locked. In that case, when you try to open it again, Cadence thinks the cell is still being edited and doesn't let you change it. If this happens, here's how you can unlock the design:

    • Find the path to the affected cell. Just try to open it and CIW will report the path.

    • Build the following expression in the CIW prompt:
      ddLockFree(ddLockPath("path to affected file"))


    The locking service can take a long time to process the request. If you still have problems opening cells, try the following:

    • Exit from Cadence.

    • At the shell prompt, type: setenv CLS_CDSD_COMPATIBILITY_LOCKING NO

    • Restart Cadence and repeat the above ddLockFree command.

  2. Recovering simulation data:
    If a spectreS simulation is interrupted for any reason (power glitch, crash, etc), there is a way to continue the simulation from the point where it broke.

    • Go down to the directory ~/simulation/cellname/spectreS/schematic/netlist, where cellname is the cell schematic that you were simulating.

    • Edit the file runSpectre, and add the option +recover to the spectre command line.

    • Invoke spectreS by typing runSpectre at the shell prompt. Spectre will continue the simulation starting from where it was interrupted.

    • Once the simulation finishes, the results can be loaded back into Analog Artist by selecting Results->Select in the menu.


    Important: Spectre will not append to the previous data file. It will create a new one. Therefore, before restarting the simulation, you should save the previous data using the Results->Save Results menu option.

  3. Giving names to the wires:
    Sometimes a design can have many connections. Connecting terminals that are far apart or in awkward places can be difficult and can make the schematic hard to understand.
    It's easier to draw small pieces of wire on the terminals and to give them the same name. Then, Design Framework II will consider that the terminals are connected to the same net.
    To name wires, do the following:

    Add->Wire Name
    Type the wire name, and click on the net.

    • Looking at transistor parameters: (for spectreS only)
      If you want to know a specific DC operating point parameter for a transistor (gm, vdsat, etc), follow these instructions:
      In the Analog Artist Simulation window, select:

      Tools->Results Browser
      Click OK in the project directory form.


        The results browser window opens. This window can be used to access any information related with the simulation. For example, to find the gm of a transistor, follow this path:

        schematic->psf->Run1->opBegin.info->[transistor]->gm


          The results marked in yellow can be selected and pasted in the calculator window (with the left mouse button), or directly in the waveform window (with the right mouse button), depending on their nature.

        • Changing the number of digits displayed:
          There is no menu command to do this. You have to use a SKILL command (SKILL is the language on which Cadence is supported).
          In the CIW (or log window), type:

          aelPushSignifDigits(8)
          ...and press return. Make sure you type the right capital letters.


            This will change the number of significant digits to 8.